Command
Icon
Function
ChipPlanner
Displays the placement of I/O and logic macros in your chip in the Tools window
PinEditor
Displays the pin out in the Tools window
NetlistViewer
Displays the netlist in the Tools window
I/O Attribute Editor
Displays the attributes in your design in the Tools window
LogicalCone
Displays the last created Logical cone in the Tools window
Active Lists
Displays a submenu of choices:
<User-defined lists> - displays user-defined lists
<Pre-defined lists> - displays any pre-defined lists such as Unassigned Macros, Unassigned I/Os, etc.
More Lists - displays a dialog box in which you can choose to create a new list, edit a list, copy a list, or delete a list.
DRC
Runs the Prelayout Checker to ensure that the design can be placed and routed
I/O Bank Assigner
Assigns a voltage to every I/O bank that does not have a voltage assigned to it and if required, a VREF pin