Flash Memory Block output files (from SmartGen)

When you click Generate the complete system, SmartGen generates the following files; they are saved in your SmartGen project directory.

HDL Source Files

<user_name>.vhd/.v – Top level design that combines all the blocks together

<user_name>_init_wrapper.vhd/.v – Initialization and configuration instantiation wrapper for this design

<Vhdl>/<Verilog>/address_gen.vhd/v - Soft IP

<Vhdl>/<Verilog>/init_sm.vhd/v – Soft IP

<Vhdl>/<Verilog>/nvm_ctl.vhd/v – Soft IP

<Vhdl>/<Verilog>/save_sm.vhd/v – Soft IP

<Vhdl>/<Verilog>/user_clk_sel.vhd/v -Soft IP

<Vhdl>/<Verilog>/user_ctl.vhd/v – Soft IP

<Vhdl>/<Verilog>/user_valid.vhd/v – Soft IP

<Vhdl>/<Verilog>/numbits.vhd/v – package file

Memory Files

<user_name>.mem - Non-volatile memory file

Configuration Files

<user_name>.cfg – Captures information about the settings that were specified for the system.

<user_name>.gen – SmartGen project file; stores information about your NVM so that you can save your settings.

<user_name>.cxf – SmartGen core configuration file that contains information required by Libero IDE for file management.

Log Files

<user_name>.log