Note: To enter an argument on a separate line, you must enter a backslash (\) character at the end of the preceding line of the command.
set_io portname [-pinname value][-fixed value][-iostd value][-out_drive value][-slew value][-res_pull value][-in_delay value][-out_load value][-register value]
portname
Specifies the portname of the I/O macro to set.
-pinname value
Assigns the I/O macro to the specified pin.
-fixed value
Locks or unlocks the location of this I/O. Locked pins are not moved during layout. Therefore, locking this I/O ensures that the specified pin location is used during place-and-route. If this I/O is not currently assigned, then this argument has no effect. The following table shows the acceptable values for the -fixed attribute:
|
Value |
Description |
|
yes |
The location of this I/O is locked |
|
no |
The location of this I/O is unlocked |
-iostd value
Sets the I/O standard for this macro. Choosing a standard allows the software to set other attributes such as the slew rate and output loading. If the voltage standard used with the I/O is not compatible with other I/Os in the I/O bank, then assigning an I/O standard to a port will invalidate its location and automatically unassign the I/O. The following table shows the acceptable values for Axcelerator devices:
|
Value |
Description |
|
LVTTL |
(Low-Voltage TTL) A general purpose standard (EIA/JESDSA) for 3.3V applications. It uses an LVTTL input buffer and a push-pull output buffer. |
|
LVCMOS25 |
(Low-Voltage CMOS for 2.5 Volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 2.5V applications. |
|
LVCMOS18 |
(Low-Voltage CMOS for 1.8 Volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 1.8V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer. |
|
LVCMOS15 |
(Low-Voltage CMOS for 1.5 volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 1.5V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer. |
|
LVDS |
A moderate-speed differential signalling system, in which the transmitter generates two different voltages which are compared at the receiver. It requires that one data bit be carried through two signal lines; therefore, you need two pins per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350mV (millivolts). Axcelerator devices contain dedicated circuitry supporting a high-speed LVDS standard that has its own user specification. |
|
LVPECL |
PECL is another differential I/O standard. It requires that one data bit is carried through two signal lines; therefore, two pins are needed per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 850mV. When the power supply is +3.3V, it is commonly referred to as low-voltage PECL (LVPECL). |
|
PCI |
(Peripheral Component Interface) Specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be 5V-compliant for most families, excluding ProASIC3/E families. |
|
PCIX |
(Peripheral Component Interface Extended) An enhanced version of the PCI specification that can support higher average bandwidth; it increases the speed that data can move within a computer from 66 MHz to 133 MHz. PCI-X is backwards compatible, which means that devices can operate at conventional PCI frequencies (33 MHz and 66 MHz). PCI-X is also more fault tolerant than PCI. |
|
HSTLI |
(High-Speed Transceiver Logic) A general-purpose, high-speed 1.5V bus standard (EIA/JESD 8-6). It has four classes, of which Actel supports Class I for Axcelerator devices. It requires a differential amplifier input buffer and a push-pull output buffer. |
|
SSTL3I |
(Stub Series Terminated Logic for 3.3V) A general-purpose 3.3V memory bus standard (JESD8-8). It has two classes, of which Actel supports both. It requires a differential amplifier input buffer and a push-pull output buffer. |
|
SSTL3II |
See SSTL3I above. |
|
SSTL2I |
(Stub Series Terminated Logic for 2.5V) A general-purpose 2.5V memory bus standard (JESD8-9). It has two classes, of which Actel supports both. It requires a differential amplifier input buffer and a push-pull output buffer. |
|
SSTL2II |
See SSTL2I above. |
|
GTLP33 |
(Gunning Transceiver Logic Plus) A high-speed bus standard (JESD8.3). It requires a differential amplifier input buffer and an open-drain output buffer. Even though output is open-drain, Axcelerator, ProASIC3, and ProASIC3E support still needs the VCCI to be connected to 2.5V or 3.3V. |
|
GTLP25 |
See GTLP33 above. |
-out_drive value
Sets the I/O output drive strength in mA. This argument is used only for LVTTL, PCI, and PCIX standards. The LVTTL standard supports all four strengths. For PCI, it only supports the 16 mA. For PCIX, it only supports the 12 mA. The following table shows the acceptable values for the -out_drive attribute:
|
Value |
Description |
|
8 |
Sets the output drive strength to 8mA |
|
12 |
Sets the output drive strength to 12mA |
|
16 |
Sets the output drive strength to 16mA |
|
24 |
Sets the output drive strength to 24mA |
-slew value
Sets the output slew rate. Slew control affects only the falling edges. Rising edges are not affected. This attribute is only available for LVTTL, PCI, and PCI outputs. For LVTTL, it can either be high or low. For PCI and PCIX, it can only be set to high. The following table shows the acceptable values for the -slew attribute:
|
Value |
Description |
|
high |
Sets the I/O slew to high |
|
low |
Sets the I/O slew to low |
-res_pull value
Allows you to include a weak resistor for either pull-up or pull-down of the input buffer. The following table shows the acceptable values for the -res_pull attribute:
|
Value |
Description |
|
up |
Includes a weak resistor for pull-up of the input buffer |
|
down |
Includes a weak resistor for pull-down of the input buffer |
|
none |
Does not include a weak resistor |
-in_delay value
Turns the input I/O delay on or off. The value of this delay is set on a bank-wide basis either by using the set_iobank PDC command or from the I/O Banks Settings dialog box in ChipPlanner or PinEditor. Refer to the Axcelerator datasheet for more details. The following table shows the acceptable values for the -in_delay attribute:
|
Value |
Description |
|
on |
Turns the input I/O delay on |
|
off |
Turns the input I/O delay off |
-out_load value
Determines what Timer will use as the loading on the output pin. This attribute applies only to outputs. You can enter a capacitive load as an integral number of picofarads (pF). The default is 35pF.
-register value
Specifies whether the register will be combined into the I/O. If this option is yes, the combiner combines the register into the I/O module if possible. This option overrides the default setting in the Compile options. I/O registers are off by default. The following table shows the acceptable values for the -register attribute:
|
Value |
Description |
|
yes |
Register combining is allowed on this I/O |
|
no |
Register combining is not allowed on this I/O |
If an argument is not specified, the value is not changed, as long as it is consistent with other settings. If setting an attribute invalidates the I/Os location, then the I/O is unplaced.
When using this command in an auxiliary PDC file, the -register argument is not honored. To combine a given I/O with the register without losing your floorplan, you must open PinEditor and select the one you need to combine and rerun compile.
set_io REG_RBB_OUT_15_ -iostd LVTTL -res_pull up -in_delay on -pinname J18 -fixed yes
set_io ADDOUT2 \
-iostd PCI \
-register yes \
-out_drive 16 \
-slew high \
-out_load 10 \
-pinname T21 \
-fixed yes