set_io (ProASIC3)

Sets the attributes of an I/O for ProASIC3 families. You can use the set_io command to assign an I/O technology, the I/O attributes, assign, or lock the I/O at a given pin location.

 

set_io portname [-pinname value][-fixed value][-iostd value][-out_drive value][-slew value][-res_pull value][-out_load value][-skew value][-register value]

Arguments

portname

Specifies the portname of the I/O macro to set.

 

-pinname value

Assigns the I/O macro to the specified pin.

 

-fixed value

Locks or unlocks the location of this I/O. Locked pins are not moved during layout. Therefore, locking this I/O ensures that the specified pin location is used during place-and-route.  If this I/O is not currently assigned, then this argument has no effect. The following table shows the acceptable values for the -fixed attribute:

 

Value

Description

yes

The location of this I/O is locked

no

The location of this I/O is unlocked

 

-iostd value

Sets the I/O standard for this macro. Choosing a standard allows the software to set other attributes such as the slew rate and output loading. If the voltage standard used with the I/O is not compatible with other I/Os in the I/O bank, then assigning an I/O standard to a port will invalidate its location and automatically unassign the I/O. The following table shows the acceptable values for the -iostd attribute for ProASIC3 devices:

 

Value

Description

LVTTL

(Low-Voltage TTL) A general purpose standard (EIA/JESDSA) for 3.3V applications. It uses an LVTTL input buffer and a push-pull output buffer.

LVCMOS33

(Low-Voltage CMOS for 3.3 Volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 3.3V applications.

LVCMOS25_50

(Low-Voltage CMOS for 2.5 and 5.0 Volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 2.5V and 5.0V applications.

LVCMOS18

(Low-Voltage CMOS for 1.8 Volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 1.8V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer.

LVCMOS15

(Low-Voltage CMOS for 1.5 volts) An extension of the LVCMOS standard (JESD 8-5) used for general-purpose 1.5V applications. It uses a 3.3V-tolerant CMOS input buffer and a push-pull output buffer.

LVDS

A moderate-speed differential signalling system, in which the transmitter generates two different voltages which are compared at the receiver. It requires that one data bit be carried through two signal lines; therefore, you need two pins per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350mV (millivolts).

LVPECL

PECL is another differential I/O standard. It requires that one data bit is carried through two signal lines; therefore, two pins are needed per input or output. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 850mV. When the power supply is +3.3V, it is commonly referred to as low-voltage PECL (LVPECL).

PCI

(Peripheral Component Interface) Specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be 5V-compliant for most families, excluding ProASIC3/E families.

PCIX

(Peripheral Component Interface Extended) An enhanced version of the PCI specification that can support higher average bandwidth; it increases the speed that data can move within a computer from 66 MHz to 133 MHz. PCIX is backward-compatible, which means that devices can operate at conventional PCI frequencies (33 MHz and 66 MHz). PCIX is also more fault tolerant than PCI.

 

-out_drive value

Sets the strength of the output buffer to 2, 4, 6, 8, 12, or 16 in mA, weakest to strongest. The list of I/O standards for which you can change the output drive and the list of values you can assign for each I/O standard is family-specific. Not all I/O standards have a selectable output drive strength. Also, each I/O standard has a different range of legal output drive strength values. The values you can choose from depend on which I/O standard you have specified for this command. See the "Slew and Out_drive Settings" table under "Exceptions" in this topic for possible values. Also, refer  to the ProASIC3 datasheet for more information. The following table shows the acceptable values for the -out_drive attribute:

 

Value

Description

2

Sets the output drive strength to 2mA

4

Sets the output drive strength to 4mA

6

Sets the output drive strength to 6mA

8

Sets the output drive strength to 8mA

12

Sets the output drive strength to 12mA

16

Sets the output drive strength to 16mA

 

-slew value

Sets the output slew rate. Slew control affects only the falling edges. Rising edges are not affected. Not all I/O standards have a selectable slew. Whether you can use the slew attribute depends on which I/O standard you have specified for this command. For ProASIC3 devices, this attribute is only available for LVTTL, LVCMOS33, LVCMOS25_50, LVCMOS18, and LVCMOS15 outputs. For any of these I/O standards, the slew can be either high or low. The default is high. See the "Slew and Out_drive Settings" table under "Exceptions" in this topic. Also, refer to the ProASIC3 datasheet for more information. The following table shows the acceptable values for the -slew attribute:

 

Value

Description

high

Sets the I/O slew to high

low

Sets the I/O slew to low

 

-res_pull value

Allows you to include a weak resistor for either pull-up or pull-down of the input buffer. Not all I/O standards have a selectable resistor pull option. The following table shows the acceptable values for the -res_pull attribute:

 

Value

Description

up

Includes a weak resistor for pull-up of the input buffer

down

Includes a weak resistor for pull-down of the input buffer

none

Does not include a weak resistor

 

-out_load value

Determines what Timer will use as the loading on the output pin. This attribute applies only to outputs. You can enter a capacitive load as an integral number of picofarads (pF). Specify an integer between 0 and 1023pF. The default is 35pF.

 

-skew value

Specifies whether there is a fixed additional delay between the enable/disable time for a tristatable I/O. (A tristatable I/O is an I/O with three output states: high, low, and high impedance.) The following table shows the acceptable values for the -skew attribute:

 

Value

Description

on

Yes, there is a fixed additional delay

off

No, there is not a fixed additional delay

 

-register value

Specifies whether the register will be combined into the I/O. If this option is yes, the combiner combines the register into the I/O module if possible. This option overrides the default setting in the Compile options. I/O registers are off by default. The following table shows the acceptable values for the -register attribute:

 

Value

Description

yes

Register combining is allowed on this I/O

no

Register combining is not allowed on this I/O

Supported Families

ProASIC3

Exceptions

Examples

set_io IO_in\[2\] -iostd LVPECL -register no -pinname 366 -fixed no

See Also    

Assign I/O to pin

reset_io

PDC syntax conventions

PDC naming conventions