The Value Change Dump (VCD) file is a simulation file. The format of this file is specified in the IEEE 1364 standard.
You can generate a VCD file with a VHDL simulator using the following commands:
vcd file example.vcd
vcd add -r *
run 1 us
This example creates a VCD file example.vcd, adds all signals recursively, and then runs the simulation for one micro second.
Note: SmartPower has been validated with VCD files generated by ModelSim. However, you may use any Verilog/VHDL simulator that offers a VCD dump feature.
Refer to the user manual of your simulation tool for more information on how to generate a VCD file.
To import a VCD file:
From the File
menu in Designer, select Import Auxiliary Files. Click Add to browse to your VCD file and select
it. When you have selected a VCD file, click OK
to continue.
If you have not yet completed the layout of the design, the design
software guides you through place-and-route so that you can import the
VCD file. In order to successfully annotate your VCD values to the design,
Designer must complete place-and-route even if you generated your VCD
file using timing simulation (post-layout).
You may wish to import multiple VCD files. If these files conflict
(attempt to set a different frequency for the same net of your design,
for example), the latest imported value takes precedence.
Specify your VCD import
options. Use the VCD Import Options
window to specify the instance name of your design in the simulation testbench
(the instance name is the instance name of your design instantiated in
the simulation testbench). For example, the instance name of the design
top_comp in the following verilog test-bench is inst.
module test;
reg [3:0] DataA, DataB;
wire AGEB;
top_comp inst(DataA, DataB, AGEB);
initial
begin
end;
endmodule;
It also possible to identify the instance name of your design in the
VCD file. You have to look for a line starting with the keyword $scope.
For example, the instance name of the design top_comp in the following
VCD file is inst.
$date
Oct 18, 2001 16:02:16
$end
$version
VERILOG-XL 3.30.p001
$end
$timescale
100ps
$end
$scope module inst $end
Click OK to continue.
Check the Log
window for notification that you successfully imported the VCD file (The
Import command succeeded...). Even
if the Import command succeeds, Actel recommends that you use SmartPower
to verify which of the pins have been affected after you import the file.
Verify results of the imported file in the Activity tab screen in SmartPower. To view the results of your imported VCD file, launch SmartPower and navigate to the Activity tab screen to view pins with annotated switching activities. If your file was imported successfully, you will see a long list of pins with annotated switching activity and specific individual frequencies.
It may be that some pins of your design are not annotated by a VCD import command. This happens if you simulate a pre-synthesis netlist; it is normal because not all logic elements are in the pre-synthesis netlist. Thus, for accurate power estimation, it is better to run post-layout simulation with a back-annotated netlist.