Actual time in nanoseconds at which the data arrives at a sink pin when considering the propagation delays across the path.
Two signals that are not related to each other. Signals not related to the clock are usually asynchronous.
The clock edge that triggers the capture of data at the end point of a path.
A periodic signal that captures data into sequential elements.
A path with the maximum delay between a starting point and an end point. In the presence of a clock constraint, the worst critical path between registers in this clock domain is the path with the worst slack.
The standard method for verifying design functionality and performance. Both pre-layout and post-layout timing analysis can be performed via the SDF interface.
See timing exception.
Clock sources that can be traced back unambiguously from the clock pin of the registers they deserve, including the output of a DLL or PLL.
A set of limitations applied to object names in timing analysis to generate target specific sets.
The clock edge that triggers the release of data from a starting point to be captured by another clock edge at an end point.
Timing characteristic of a path between two registers. It indicates how fast the clock will run when this path is the most critical one. The minimum period value takes into consideration both the skew and the setup on the receiving register.
A sequence of elements in the design that identifies a logical flow starting at a source pin and ending at a sink pin.
An expansion of the path that shows all the nets and cells between the source pin and the sink pin.
A collection of paths.
See path set.
The state of the design after running layout in which the placement and routing information are available for the whole design.
Pins or ports connected to the clock pins of sequential elements that the Static Timing Analysis (STA) tool cannot determine whether they are is enabled sources or clock sources. This type of clock is generally associated with the use of gated clocks.
The state of the design before running layout is run in which the placement and routing information are not available.
Time at which the data is required to be at a sink pin to avoid being in violation.
See timing requirement.
The time in nanoseconds relative to a clock edge during which the data at the input to a sequential element must remain stable.
The pin located at the end of the timing path. This pin is usually the one where arrival time and required time are evaluated for path violation.
The difference between the clock insertion delay to the clock pin of a sink register and the insertion delay to the clock pin of a source register.
The difference between the arrival time and the required time at a specific pin, generally at the data pin of a sequential component.
The time needed for a signal to transition from one logic level to another.
The pin located at the beginning of a timing path.
Standard Delay Format, a standard file format used to store design data suited for back-annotation.
An efficient technique to identify timing violations in a design and to ensure that all timing requirements are met. It is well suited for traditional synchronous designs. The main advantages are that it does not require input vectors, and it exclusively covers all possible paths in the design in a relatively short run-time.
A requirement or limitation on the design to be satisfied during the design implementation.
An exception to a general requirement usually applied on a subset of the objects on which the requirement is applied.
A constraint on the design usually determined by the specifications at the system level.
Wire Load Model. A timing model used in pre-layout to estimate a net delay based on the fan-out.