Generally, you would like to set clock constraints on clocks for which you have a specified requirement. The absence of violations would then indicate that this clock will be able to run at least at the specified frequency. However, in the absence of such requirements, you may still be interested in computing the maximum frequency of a specific clock domain.
To obtain the maximum clock frequency, a static timing analysis tool computes the minimum period for each path between two sequential elements. To compute the minimum period, the tool evaluates the maximum data path delay and the minimum skew between the two elements, as well as the setup on the receiving sequential element. It also considers the polarity of each sequential element. The maximum frequency is then the inverse of the smallest value among the minimum period of all the paths in the clock domain. The path responsible for limiting the frequency of a given clock is called the critical path.