Timing Report Max Delay Analysis
Timer Version 2.0
Actel Corporation - Actel Designer Software Release 6.2 (Version 6.2.0.0)
Copyright (c) 1989-2005
Date: Tue Mar 22 10:33:03 2005
Design: test
Family: Axcelerator
Die: AX250
Package: 352 CQFP
Temperature: MIL
Voltage: MIL
Speed Grade: -1
Design State: Pre-Layout
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SUMMARY
Clock Domain: Osc_Clk_60Mhz
Period (ns): 5.492
Frequency (MHz): 182.083
Required Period (ns): N/A
Required Frequency (MHz): N/A
External Setup (ns):
External Hold (ns):
Min Clock-To-Out (ns):
Max Clock-To-Out (ns):
Clock Domain: Perph_BitClk
Period (ns): 2.770
Frequency (MHz): 361.011
Required Period (ns): N/A
Required Frequency (MHz): N/A
External Setup (ns):
External Hold (ns):
Min Clock-To-Out (ns):
Max Clock-To-Out (ns):
In->Out:
Min Delay (ns):
Max Delay (ns):
END SUMMARY
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Clock Domain Osc_Clk_60Mhz
SET reg->reg
Path 1
From: machine_5/state_h/stateZ0Z_4:CLK
To: machine_5/sync_tdm_rst_l:D
Delay (ns): 5.178
Slack (ns):
Arrival (ns): 9.079
Required (ns):
Setup (ns): 0.314
Minimum Period (ns): 5.492
Path 2
From: machine_4/state_h/state_2:CLK
To: machine_5/src_en_l_1/U1/U0:D
Delay (ns): 5.166
Slack (ns):
Arrival (ns): 9.067
Required (ns):
Setup (ns): 0.298
Minimum Period (ns): 5.464
Expanded Path 1
Total(ns) Op Delay(ns) Pin Name (edge)
Type/name
0.000 Osc_Clk_60Mhz
+ 3.901 clock network
3.901 machine_5/state_h/stateZ0Z_4:CLK (r)
+ 0.910 cell: ADLIB:DFEG
4.811 machine_5/state_h/stateZ0Z_4:Q (r)
+ 0.668 net: machine_5/state_4
5.479 machine_5/m8_0_a2_0:V1 (r)
+ 0.985 cell: AFGLIB:i894
6.464 machine_5/m8_0_a2_0:Y (r)
+ 0.215 net: machine_5/y_8
6.679 machine_5/m8_0_m3:V3 (r)
+ 0.985 cell: AFGLIB:a798
7.664 machine_5/m8_0_m3:Y (r)
+ 0.215 net: machine_5/y_12
7.879 machine_5/m8_0:V0 (r)
+ 0.985 cell: AFGLIB:a528
8.864 machine_5/m8_0:Y (r)
+ 0.215 net: machine_5/y_16
9.079 machine_5/sync_tdm_rst_l:D (r)
9.079 data arrival time
________________________________________________________
10.000 Osc_Clk_60Mhz
+ 3.901 clock network
13.901 machine_5/sync_tdm_rst_l:CLK (r)
- 0.314 Library setup: ADLIB:DFEG
13.587 machine_5/sync_tdm_rst_l:D
13.587 data required time
________________________________________________________
13.587 data required time
-
9.079 data arrival time
4.508 slack
END SET reg->reg