Constraint verification is an essential task that timing analyzers help you achieve. The most popular constraint verification is to ensure that the design functions as specified at the required clock frequency. This is traditionally known as the setup and hold check.
Setup check specifies when data is required to be present at the input of a sequential component in order for the clock to capture this data effectively into the component. Timing analyzers evaluate the setup check as a maximum timing budget allowed between adjacent sequential elements. For more details on how setup check is processed, refer to Arrival time, required time, and slack.