SmartTime provides multiple views for timing constraint editing and timing analysis. In the Timing Constraints View, you can add or modify your timing requirements and timing exceptions using easy to use visual dialogs. The Timing Analysis View enables you to browse through the design’s various clock domains to examine the timing paths and identify those that violate the timing requirements.
Using the Timing Analysis View, you can set constraints on a specific pin (for example, clock constraint) or on a specific set-of-paths (for example, maximum delay constraint). Whether you set a given constraint from the Timing Constraints View or the Timing Analysis View, SmartTime displays the same visual dialog to preserve consistency across the tool.
SmartTime supports a range of timing constraints to provide useful analysis and efficient timing-driven layout. Most constraints that can be generated by Synthesis tools such as clocks, input arrival times, and output required times are automatically passed to SmartTime in an SDC file. You can edit these constraints in the Timing Constraints Editor.
SmartTime also includes a constraint checker that validates the constraints in the database.
SmartTime provides a selection of analysis types that enable you to:
Find the minimum cycle time that does not result in a timing violation
Identify paths with timing violations
Analyze delays of paths that have no timing constraints
Perform inter-clock domain timing verification
Perform maximum and minimum delay analysis for setup and hold checks
In order to improve the accuracy of the results, during timing analysis, SmartTime evaluates clock skew by individually computing clock insertion delays for each register.
SmartTime checks the timing requirements for violations while evaluating timing exceptions such as multicycle or false paths.
SmartTime provides a highly interactive user interface that enables you to navigate directly to the paths responsible for violating your timing requirements. You can then make changes, such as modifying your constraints or setting timing exceptions and running Layout with these changes to achieve timing closure.
The SmartTime user interface includes the following:
A separate Timing Constraint View where constraints are sorted by category (requirements and exceptions) and by constraint type.
A Constraint Browser that enables you to navigate through the different categories and types.
Easy-to-use visual dialogs to edit constraint parameters.
The Timing Analysis View organized by clock domain and by a pre-defined sets of paths. (Separate views for performing minimum and maximum timing analysis.)
The Domain Browser that enables you to navigate through the multiple clock domains. (The filter capabilities that can be saved in the Domain Browser.)
A customizable Paths List to select from timing information to display.
A detailed Expanded Path View.
Support for cross-probing objects and paths with NetlistViewer, ChipPlanner, and ChipEditor tools.
Customizable timing reports.
The SmartTime static timing analysis tool works very tightly with Actel’s place-and-route tool. It uses the same timing engine during Layout to evaluate critical paths and help Layout to meet your performance goals.
Therefore, timing constraints impact both analysis and Layout consistently. As a result, adding and editing your timing constraints in SmartTime is the best way to achieve the best performance. (This tightly coupled software architecture enables you to achieve timing closure quickly.)
Note: The SmartTime and Layout interaction is not available for all families supported by SmartTime. For details, refer to the Design Constraints Guide.