Using the timing analysis view, you also have the capability of setting constraints on a specific pin such as a clock constraint or on a specific set-of-paths like maximum delay constraint. The same constraint visual dialog is displayed to preserve consistency across the tool.
SmartTime supports a range of timing design constraints to provide useful analysis and efficient timing driven layout capabilities. Most constraints that can be generated by Synthesis tools such as clocks, input arrival times and output setup and hold times are automatically passed to SmartTime in an SDC . Constraints and are accessible in the editor.
SmartTime also includes a constraint checker that validates the consistency of the constraint database.