Path delays are computed by adding delay values across a chain of gates and interconnect. SmartTime uses this main information to check for timing violations. Traditionally, timing paths are presented by static timing analysis tools in four categories or sets:
Paths between sequential components internal to the design. SmartTime displays this category under the Register to Register set of each displayed clock domain.
Paths that start at input ports and end at sequential components internal to the design. SmartTime displays this category under the External Setup and External Hold sets of each displayed clock domain.
Paths that start at sequential components internal to the design and end at output ports. SmartTime displays this category under the Clock to Out set of each displayed clock domain.
Paths that start at input ports and end at output ports. SmartTime displays this category under the Input to Output set.