Clock Skew Analysis

The difference in the arrival times of the clock signals between two sequentially-adjacent registers (clock skew) may cause a design to malfunction with short data paths. The most efficient method to eliminate the short data path problem is to minimize the clock skew by using the low-skew global routing resources for clock signals.  

Refer to the Static Timing Analysis Using Designer's Timer application note for information on clock skew analysis (http://www.actel.com/documents/Static_Timing_Analysis.pdf).  

To measure clock skew:

1. Specify clock frequency. In order to obtain hold margin calculations, Timer requires that you specify a clock frequency. Timer uses the frequency to calculate the period, which it needs to evaluate the margin for adjacent flip-flops with alternate clock edges. If you do not enter a clock frequency in the summary tab, you will not get any results.  
   
   To enter a frequency, select the desired clock under Select Clock, and enter a frequency under required in the Summary tab. Click Set when you are done.

2. Set your Preferences in Timer. To measure clock skew, perform hold time analysis for BEST case in Shortest path mode. Set the Case in File -> Preferences.  

3. Run Violations Report. A report is available from Timer that provides a summary of timing margins for all paths in the design. From the Tools menu, choose Report Violations. This report lists the following categories:
   
   · Section Clock constraints violation
   · Section Max Delay constraints violation
   · Section Min Delay constraints violation
   
   To find a summary of hold time margin in your design for the given operating conditions, refer to the timing path listed under Section Min Delay constraints violations.
   
   The first column defines the slack for each path. Positive values represent margin, negative values represent a violation.

4. Perform detailed analysis. To see the details of a given path, go to the Paths tab in Timer. You can look for a specific path by creating a new path set for the specific path(s) you are interested in. To create a path set, choose Add set of paths from the Edit menu. Refer to the Paths tab for information on how to add a set of paths.  
   
   Once you have defined the new path set, click the set to display the path list in the lower spreadsheet. Then highlight the path you are interested in, right click and select Expand Path.  

5. Review Expanded Path window. The expand path window shows details of the calculations performed in the clock skew analysis.
   
   The margin is calculated by adding the clock propagation delay of the master register to the data path delay between the two registers. This is the data arrival time. Then the clock propagation to the slave register is subtracted from the sum, giving the final slack value. If alternate clock edges are used for adjacent registers, Timer considers the clock period accordingly.