The following terminology appears in the description of constraints for Timer.
Timing Driven Layout terminals define the starting (or source) and ending (or sink) points for a signal path. They are always I/Os or sequential elements; no intermediate combinatorial element is currently supported as a terminal.
The signal path describes a consecutive sequence of logic and nets, the first net being driven by a start terminal, and the last net driving a macro input pin of the end terminal.
A network can consist of 1 or more start terminals and 1 or more end terminals. All signal paths connecting any start terminal to any end terminal are included in the network. Only one delay value can be assigned to each defined network. Networks can be defined implicitly by a common clock (synchronous network) or explicitly by a defined set of terminals. Network and Paths are used interchangeably.
The path delay defines the sum of all the individual delays of the nets and the logic macros in the signal path.
A delay constraint defines a fixed amount of time required for a signal to propagate from all starting terminals to all ending terminals for a network.
A signal path in which the delay is considered to be infinite.
A defined intermediate point in a network that forces all paths through the defined point to be don't care paths regardless of any constraint assignment.
A terminal in a synchronous network that should be excluded from the specified clock period. The exception can remain undefined (don't care) or can be assigned a unique value in the Path Constraint Editor.