This glossary defines terms and concepts used in the Timer online help.
A terminal in a synchronous network that should be excluded from the specified clock period. The exception can remain undefined (don't care) or can be assigned a unique value in the Path Constraint Editor.
The path within a design that dictates the fastest time at which an entire design can run. This path runs from the source to a sink node such that if any activity on the path is delayed by an amount t, then the entire circuit function is delayed by time t.
A delay constraint defines a fixed amount of time required for a signal to propagate from all starting terminals to all ending terminals for a network.
An ending point, sink node, for a timing analysis path, often the data input of a synchronous element or pad.
A signal path in which the delay is considered to be infinite.
Dynamic timing analysis (simulation) has been the standard mechanism in verifying design functionality and performance. Both pre-layout and post-layout timing analysis can be performed via the SDF interface. Pre-layout timing analysis provides quick estimates of the designs performance. Post-layout timing simulation on the other hand provides accurate timing information that is appropriate for device or system level simulation.
A set of limitations or options applied to the timing analysis to more specifically target important items of interest.
A defined intermediate point in a network that forces all paths through the defined point to be don't care paths regardless of any constraint assignment.
Network. A network can consist of one or more start terminals and one or more end terminals. All signal paths connecting any start terminal to any end terminal are included in the network. Only one delay value can be assigned to each defined network. Networks can be defined implicitly by a common clock (synchronous network) or explicitly by a defined set of terminals. Network and Paths are used interchangeably.
An ordered set of elements identifying a logic flow pathway through a circuit. A path may consist of a single net or a grouping of related nets and components. There can be multiple, or parallel paths (consisting of nets and components) between the two pins. When a component is selected as part of a path, both the input pin to the component and the output pin are included in the path. A path stops when it reaches the data input of a synchronous element (flip-flop), clock, or pad. A path usually starts at the output of a synchronous element, clock, or pad.
The path delay defines the sum of all the individual delays of the nets and the logic macros in the signal path.
Groups or categories of paths are called “sets.” Path sets are displayed on the Paths tab.
The signal path describes a consecutive sequence of logic and nets, the first net being driven by a start terminal, and the last net driving a macro input pin of the end terminal
The difference between the constraint and the analyzed value, with negative slack indicating the analyzed value is greater than the constrained value.
Standard Delay Format is an industry-standard file format used for storing timing data generated by EDA tools. It is often used for simulation.
Static timing analysis is an exhaustive and convenient method of ensuring that a design meets its timing requirements. There are functions that are especially easy to analyze with the static approach. Complex functions such as a multiplier are much easier to analyze using the static approach because static analysis offers one hundred percent coverage with minimal effort compared to dynamic timing analysis. In addition, the static approach is faster for highly synchronous designs compared to dynamic timing analysis.
The area located at the bottom of an application window.
A toggle rate defines the frequency of a net or logic element relatively to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at 1/2 of the clock frequency.