Normally, Timer displays only critical paths. Critical paths are the longest paths between any of the starting points (terminals) and each ending terminal. If you would like to see the timing of all paths between any of the starting terminals and any of the ending terminals, select Paths Between Any Pair (input-to-input timing model families only) in the Path Selection area of the Preferences dialog box. Selecting Critical Paths displays only critical paths.
Asynchronous feedback paths in a design can cause paths to be reported as having excessive delays. The most common example is feedback paths through asynchronous Set or Reset pins to banks of flip-flops, like a state machine or a counter.
To exclude paths:
From the File menu, choose Preferences. The Preferences dialog box appears
Break
Paths at Register. Choose Clk/G
Pins, Clr/Pre Pins (Async)
or Data Pins of Latches to prevent
displaying paths that pass through either clock, gated, clear, preset,
or data pins of flip-flops or latches.
Note: The Break Paths at Register
option is selected by default, and the paths are excluded. Clear
the check boxes in the Timer Preferences menu to display these paths.
Click OK.