Use SmartGen to:
Create high-level modules, such as counters, multiplexors, multipliers, etc. that are optimized for Actel FPGAs.
Create system-level building blocks, such as filters, FIFOs, and memories.
These can be instantiated into your schematic, Verilog design, or HDL design.
To generate cores for your schematic:
From the Libero File menu, choose New.
In the New File dialog box, select SmartGen core, type a name, and click OK. SmartGen starts.
Select your core type. The appropriate options appear. Select a tab and fill in the fields. Click Generate to create an HDL representation of the core.
In the Save As dialog box, leave the default selections and click Save. The file is added to your Libero project; it appears in the Design Hierarchy.
Create the Symbol. In the Design Hierarchy, right-click the SmartGen module and choose Create Symbol. The symbol is created; it appears in the File Manager, under Block Symbol files.
To use the symbol, start ViewDraw.
From the Add menu, choose Component.
Select the new symbol, drag-and-drop to add it to your schematic.