Use SmartGen to:
Create high-level modules, such as counters, multiplexers, multipliers, etc. that are optimized for Actel FPGAs.
Create system-level building blocks, such as filters, FIFOs, and memories.
These can be instantiated into your schematic, Verilog design, or HDL design.
To use SmartGen with your HDL design:
From the Libero File menu, choose New.
In the New File dialog box, select SmartGen core, type a name, and click OK. SmartGen starts.
Select your core type. The appropriate options appear. Select a tab and fill in the fields. Click Generate.
In the Save As dialog box, leave the default selections and click Save. The file is added to your Libero project; it is shown in the Design Hierarchy.
Instantiate the module in your HDL design.