To access this dialog, from the Options menu, choose File Organization > Package Files.
The box that appears depends on whether you are using VHDL or Verilog.
Use the VHDL Package Files or Verilog Header Files dialog box to preserve the package file sequence. This is important if your VHDL Package Files or Verilog Header Files are interdependent.
Use the up and down arrows to specify the order, or drag the files into order. Select Simulation or Synthesis if you want the file included when simulation or synthesis is run.