The following are highlights of new features for Libero IDE v6.3. For a more complete list, see the Libero IDE v6.3 release notes.
Libero IDE v6.3 includes complete design flow support for the low-power 32-bit ARM7 RISC microprocessor core, providing:
Synthesis and verification of the ARM7 system with Synplify AE and ModelSim AE
Performance optimization and physical synthesis with PALACE AE
A high level of encryption to safeguard the ARM7 and user IP from unauthorized viewing and/or usage
Design implementation in a variety of ProASIC3 and ProASIC3E devices and packages.
SmartTime now features characterized timing for min_delays. This enhancement enables you to evaluate both setup and hold timing at the internal and chip-to-chip levels.
SmartGen now includes an Intellectual Property Catalog that enables you to view the complete list and detailed information on Actel's Intellectual Property (IP) core offering.
Libero IDE v6.3 supports the complete design flow for the new RTAX4000S – the newest and largest High-Rel FPGA device in the industry.
MultiView Navigator
For Fusion, ProASIC3/E, and Axcelerator families, the new I/O Bank Assigner runs automatically when you run Layout. The I/O Bank Assigner automatically assign technologies (VCCI voltages and VREF pins) to all I/O banks that have not been assigned a technology. You can also invoke the I/O Bank Assigner from within the MultiView Navigator.
MVN now supports SX-A and eX families.
New MVN commands help you perform several tasks with one click: Commit and Check, Lock All, Unlock All. Unassign All from Location, Unassign All from Region.
FlashPro 4.0 software enables a single FlashPro GUI to program multiple FlashPro/FlashPro3 units via USB connection. FlashPro 4.0 adds new programming functionality including a redesigned user interface, a ‘project flow’ feature for Flash programming, and serialization support. FlashPro v4.0 continues to support programming via the parallel port for both FlashPro Lite and FlashPro Programmers.