Questions & Answers

General

System Clock Management

Software and Intellectual Property

Device Configuration

 

General

What is the Angelo series?

The Angelo family series products offer the low-cost FPGAs with unique Look-up Table (LUT) logic structures, rich user resources, variety of package choices. Some of our products also contain nonvolatile memory which offers protection to users intellectual property rights. These products are your perfect choice for SOC and system modules design by replacing CPLD, ASSP and other standard logic devices.

What is the Angelo family of FPGAs?

The Agate Logics Angelo family is the first generation of the low-cost FGPA series. With the target of satisfying the demanding requirements of the global market, Agate Logic developed Angelo FPGAs for low-density logic application in industry, publication, part of consumption electronic products and other fields with high confidential requirements of intellectual property rights.

How many packages do Angelo family series products provide?

There are four types of package options available at present for Angelo family series products:
- 100 pin TQFP with 4Mbit internal flash, 16 x 16 mm package size, 56 user I/Os
- 144 pin LQFP with 4Mbit internal flash, 22 x 22 mm package size, 96 user I/Os
- 208 pin PQFP with 4Mbit internal flash, 30.6 x 30.6 mm package size, 156 user I/Os
- 208 pin PQFP without internal flash, 30.6 x 30.6 mm package size, 153 user I/Os

What is the process technology for the Angelo FPGA family?

The Angelo FPGA family is based on a low-cost 3.3-V, 0.13-µm, 1Poly 8 Metal generic process from SIMC.

What is the meaning of Angelo device ordering codes?

These ordering codes are based on the LC number inside each type of packages. For example: in AG1F4N4 F4 stands for 4096 FPGAs and N4 stands for 4Mbit flash.

What type of embedded memory and memory features do Angelo FPGAs have?

The Angelo consists of the embedded memory blocks with 9K-bit dual-port RAMs (EMB9Ks) to address on-chip memory needs. The EMB9K is a dual-port SRAM that can implement various types of memory with or without parity, including true dual-port, simple dual-port and single-port RAM. The memory blocks can be used to provide memory functions such as RAM and FIFO. There are 8 blocks of EMB9K Angelo devices.


System Clock Management

What type of system clock management solution is offered in Angelo FPGAs?

Angelo devices offer up to 16 global clocks and 2 PLLs.

What does the global clock network consist of, and what can it be used for in Angelo FPGAs?

There are 16 global clocks, which can be driven by dedicated clock pins, PLL outputs, and logic cells (LCs). Angelo devices provide up to 8 or 4 dedicated clock pins. Global clock network provides clock for Field Programmable (FP), Internal DPRAMs, and I/Os. Global clocks can be of clock control signal for FP, such as clock signal and reset signal of FP register. At the same time, global clock, asynchronous reset signal, and clock enable signal also can be driven by FP internal logic. The clock network is optimized to minimize skew, provide clock, and clear as well as reset signals to all resources inside the device.

How many dedicated global clock inputs are available per device?

Angelo devices provide up to 8 dedicated clock pins, except for the AG1F4N4L144GC7 device in the 144-pin TQFP package, which has 4 dedicated clock input pins.

How many PLLs are available in Angelo FPGAs? What PLL features are available?

Angelo devices contain two PLLs. These PLLs provide general-purpose clocks with clock multiplication and division, and internal and board level deskew function for system synchronization.

What I/O electrical standards are supported in Angelo FPGAs?

Angelo FPGAs support LVTTL and LVCMOS I/O standards. The LVTTL and LVCMOS standards have several levels of drive strength that you can control. The table below lists the single-ended I/O standards supported by Angelo FPGAs and their respective performance.


Software and Intellectual Property

What versions of the Primace design software support Angelo FPGAs?

All Angelo devices are currently supported by the powerful tools Primace 2.0.

What intellectual property (IP) cores are available for Angelo FPGAs?

Various IP cores are specifically optimized for the Angelo architecture, including the following:
- Synchronous and Asynchronous FIFO
- SDR SDRAM Controller
- UART
- PLL
- True Dual Port RAM


Device Configuration

What configuration devices are available to support Angelo FPGAs?

There is an internal flash which can be directly configured with Angelo FPGA, except for the AG1F4Q208GC7 device in the 208-pin PQFP package, which can be configured by the industry-standard SPI serial devices. These configuration devices are low cost ones with a non-volatile memory that features a simple few pin interface and a small form factor. These features make serial configuration devices an ideal solution for configuring the low-cost Angelo devices.

What is the feature of Angelo flash?

A combo flash can not only be used for the FPGA's configuration data but also user data. These two types of data, which are protected by Angelo security mechanism, will be stored in different area in the flash. More than one set of configuration data can be stored. Users utilize their preferable configuration data to configure their FPGAs.

The access from an external device to an Angelo combo flash is prohibited. Under the effective protection of read forbidden feature and special access mechanism, the information stored in the flash and users property intellectual properties will be safe.