ADDENDUM #1


     SECTION 3.1         CONNECTORS

     THE PIO-48 BOARD PROVIDES TWO CONNECTORS  FOR EACH PORT. THE FIRST 
     ONE  (J1 AND  J3) IS  A 50  PIN HEADER  DESIGNED TO  MATE WITH  AN 
     OPTIONAL RIBBON CABLE TO A SOLID  STATE RELAY I/O MODULE RACK. THE 
     SECOND CONNECTOR,  (J2 AND J4)  IS A  40 PIN HEADER  THAT CONNECTS 
     THROUGH AN OPTIONAL RIBBON CABLE TO  A DB-37 (MALE) CONNECTOR THAT 
     MATCHES THE PIN-OUT  OF THE METRABYTE PIO-12  BOARD.


     SECTION 3.2         CONNECTOR PIN-OUT

     PORT BIT                   J1,J3       J2,J4     DB-37 
                                50 PIN     40 PIN     CABLE
     _________________________________________________________________
     PORT A BIT 0                  47        36        37
                1                  45        34        36
                2                  43        32        35
                3                  41        30        34
                4                  39        28        33
                5                  37        26        32
                6                  35        24        31
                7                  33        22        30
     PORT B BIT 0                  31        19        10
                1                  29        17         9
                2                  27        15         8
                3                  25        13         7
                4                  23        11         6
                5                  21         9         5
                6                  19         7         4
                7                  17         5         3
     PORT C BIT 0                  15        20        29
                1                  13        18        28
                2                  11        16        27
                3                   9        14        26
                4                   7        12        25
                5                   5        10        24
                6                   3         8        23
                7                   1         6        22
     GROUND                        2-50      4,21,25   11,13,15
                                             29,33,37  17,19,21
     INTERRUPT INPUT               N/C       1          1
     INTERRUPT ENABLE/             N/C       3          2
     +5  VOLTS                     49        2,35      20
     -5  VOLTS                     N/C       23        12
     +12 VOLTS                     N/C       31        16
     -12 VOLTS                     N/C       27        14



ADDENDUM #2

      A) ALL OUTPUTS ARE INVERTED ON THE C LANGUAGE INTERFACE (PIO48_C.OBJ).