AN00019.TXT

Advanced Communication Board Developer's Toolkit 1995
    

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Subject: Upgrade to ESCC 85230 resolves bus timing problem

As CPU speeds and overall system performance on a PC platform increase, 
PC chip sets must become more responsive. This increased responsiveness 
may cause some incompatibilities with existing ISA cards. The following 
application note describes a specific incompatibility with an ACB card 
and Intel PCI chip sets. Although this problem may not seem straightforward
if you are not familiar with Direct Memory Access (DMA) or ISA bus 
timing, the solution to the problem is very simple.

ACB cards that use full duplex DMA utilize the Z8530 signal DTR/REQ to 
request a transmit DMA cycle. The deactivation timing of this signal is 
slightly greater that the receive DMA cycle (Z8530 signal WAIT/REQ). 
The Z8530 does not deactivate the DTR/REQ signal fast enough for some 
Intel PCI chip sets. The Z8530 SCC normally asserts DTR/REQ to signal 
the start of a transmit DMA cycle. After the character is transmitted 
by the DMA controller, the Z8530 does not deassert the DTR/REQ signal 
soon enough for the Intel PCI controller. The PCI chip set recognizes 
the DTR/REQ signal as another DMA request and an additional DMA cycle 
is executed. This problem is corrected in the Z85230 Enhanced Serial
Communication Controller (ESCC). The Z85230 ESCC has improved DTR/REQ
deactivation timing that allows a transmit DMA cycle to have identical 
timing as a receive DMA cycle. The Z85230 is pin compatible with the
Z8530 so it is a "drop-in" upgrade. To enable the specific DTR/REQ 
timing features of the Z85230 software must program WR7 PRIME bit D4
to 1 (i.e. 10 hex). Please refer to the SCC / ESCC User manual for 
details regarding WR7 PRIME access and specific DTR/REQ timing.