/*******************************************************************/ /* Advanced Communication Board Developer Toolkit 1995 */ /* */ /* (c)Copyright Sealevel Systems Incorporated, 1993 - 1995 */ /* */ /*******************************************************************/ /* For use with the Advanced Communication Boards Z8530.h, This */ /* file contains defines and equates that are relevant to the */ /* Zilog Z8530 SCC and Z85230 ESCC (Z85C30 also). */ /* NOTE: Most register definitions should be compatible */ /* with the Intel 82530 or the AMD Am8530. */ /*******************************************************************/ /*******************************************************************/ /* Write Registers */ /*******************************************************************/ #define WR0 0x00 #define WR1 0x01 #define WR2 0x02 #define WR3 0x03 #define WR4 0x04 #define WR5 0x05 #define WR6 0x06 #define WR7 0x07 #define WR8 0x08 #define WR9 0x09 #define WR10 0x0A #define WR11 0x0B #define WR12 0x0C #define WR13 0x0D #define WR14 0x0E #define WR15 0x0F /*******************************************************************/ /* Read Registers */ /*******************************************************************/ #define RR0 0x00 #define RR1 0x01 #define RR2 0x02 #define RR3 0x03 #define RR10 0x0A #define RR12 0x0C #define RR13 0x0D #define RR15 0x0F #ifdef Z85230 #define RR4 0x04 #define RR5 0x05 #define RR9 0x09 #define RR11 0x0B #define RR14 0x0E #ifdef Z85C30 #define RR6 0x06 #define RR7 0x07 #endif #endif /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 0 */ /*******************************************************************/ #define RESET_EXT_STATUS_INT 0x10 #define SEND_ABORT 0x18 #define ENABLE_INT_NEXT_RX_CHAR 0x20 #define RESET_TX_INT_PEND 0x28 #define ERROR_RESET 0x30 #define RESET_HIGHEST_IUS 0x38 #define NULL_CODE 0x00 #define RESET_RX_CRC 0x40 #define RESET_TX_CRC 0x80 #define RESET_TX_UR_EOM 0xC0 /*******************************************************************/ /* 8530 Write Register 1 */ /*******************************************************************/ #define WAIT_DMA_DISABLE 0x00 #define INT_DISABLE 0x00 #define EXT_INT_ENABLE 0x01 #define TX_INT_ENABLE 0x02 #define PARITY_IS_SP_COND 0x04 #define RX_INT_DISABLE 0x00 #define RX_INT_1ST_CHAR_SP_COND 0x08 #define RX_INT_ALL_CHAR_SP_COND 0x10 #define RX_INT_SP_COND 0x18 #define WAIT_DMA_RX 0x20 #define WAIT_DMA_TX 0x00 #define WAIT_DMA_FUNCTION 0x40 #define WAIT_REQ_ENABLE 0x80 /*******************************************************************/ /* 8530 Write Register 2 */ /*******************************************************************/ /* This register is used as a general purpose scratch */ /* register on the ACB cards. */ /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 3 */ /*******************************************************************/ #define RX_ENABLE 0x01 #define SYNC_CHAR_LOAD_INHIBIT 0x02 #define ADDRESS_SEARCH_MODE 0x04 #define RX_CRC_ENABLE 0x08 #define ENTER_HUNT_MODE 0x10 #define AUTO_ENABLES 0x20 #define RX_5_BITS 0x00 #define RX_6_BITS 0x80 #define RX_7_BITS 0x40 #define RX_8_BITS 0xC0 /*******************************************************************/ /* 8530 Write Register 4 */ /*******************************************************************/ #define PARITY_ENABLE 0x01 #define PARITY_DISABLE 0x00 #define PARITY_EVEN 0x02 #define PARITY_ODD 0x00 #define SYNC_MODE_ENABLE 0x00 #define STOP_BIT_1 0x04 #define STOP_BIT_1_5 0x08 #define STOP_BIT_2 0x0C #define SYNC_8_BIT 0x00 #define SYNC_16_BIT 0x10 #define SDLC_MODE 0x20 #define EXTERNAL_SYNC 0x30 #define X1_CLOCK 0x00 #define X16_CLOCK 0x40 #define X32_CLOCK 0x80 #define X64_CLOCK 0xC0 /*******************************************************************/ /* 8530 Write Register 5 */ /*******************************************************************/ #define TX_CRC_ENABLE 0x01 #define RTS_ON 0x02 #define CRC_16 0x04 #define CRC_SDLC 0x00 #define TX_ENABLE 0x08 #define SEND_BREAK 0x10 #define TX_5_BITS 0x00 #define TX_6_BITS 0x40 #define TX_7_BITS 0x20 #define TX_8_BITS 0x60 #define DTR_ON 0x80 /*******************************************************************/ /* 8530 Write Register 6 */ /*******************************************************************/ /* This register holds the sync character or SDLC address */ /* flag */ /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 7 */ /*******************************************************************/ /* This register holds the sync character or SDLC flag */ /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 7 Prime (ESCC and CMOS only) */ /*******************************************************************/ #ifdef Z85230 #define WR7_PRIME 0x07 #define AUTO_TX_FLAG 0x01 #define AUTO_EOM_RST 0x02 #define AUTO_RTS_DEACT 0x04 #define RX_FIFO_LEVEL 0x08 #define DTR_REQ_TIMING 0x10 #define TX_FIFO_LEVEL 0x20 #define EX_READ_ENABLE 0x40 #endif /*******************************************************************/ /* 8530 Write Register 8 */ /*******************************************************************/ /* This register is the transmit buffer register */ /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 9 */ /*******************************************************************/ #define VIS 0x01 #define NV 0x02 #define DLC 0x04 #define MI_ENABLE 0x08 #define MI_DISABLE 0x00 #define STATUS_HIGH 0x10 #ifdef Z85230 #ifdef Z85C30 #define SW_INT_ACK 0x20 #endif #endif #define NO_RESET 0x00 #define CH_B_RESET 0x40 #define CH_A_RESET 0x80 #define FORCE_HW_RESET 0xC0 /*******************************************************************/ /* 8530 Write Register 10 */ /*******************************************************************/ #define SYNC_6_BIT 0x01 #define LOOP_MODE 0x02 #define ABORT_ON_UNDERRUN 0x04 #define MARK_IDLE 0x08 #define GO_ACTIVE_ON_POLL 0x10 #define NRZ 0x00 #define NRZI 0x20 #define FM1 0x40 #define FM0 0x60 #define CRC_PRESET_TO_ZERO 0x00 #define CRC_PRESET_TO_ONE 0x80 /*******************************************************************/ /* 8530 Write Register 11 */ /*******************************************************************/ #define TRXC_OUT_XTAL 0x00 #define TRXC_OUT_TX_CLOCK 0x01 #define TRXC_OUT_BRG 0x02 #define TRXC_OUT_DPLL_OUT 0x03 #define TRXC_IS_OUTPUT 0x04 #define TX_CLK_RTXC_PIN 0x00 #define TX_CLK_TRXC_PIN 0x08 #define TX_CLK_BRG 0x10 #define TX_CLK_DPLL_OUT 0x18 #define RX_CLK_RTXC_PIN 0x00 #define RX_CLK_TRXC_PIN 0x20 #define RX_CLK_BRG 0x40 #define RX_CLK_DPLL_OUT 0x60 /*******************************************************************/ /* 8530 Write Register 12 */ /*******************************************************************/ /* This Register sets the Lower Byte of Time Constant */ /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 13 */ /*******************************************************************/ /* This Register sets the Upper Byte of Time Constant */ /*******************************************************************/ /*******************************************************************/ /* 8530 Write Register 14 */ /*******************************************************************/ #define BRG_ENABLE 0x01 #define BRG_DISABLE 0x00 #define BRG_SOURCE_PCLK 0x02 #define BRG_SOURCE_RTXC 0x00 #define REQUEST_FUNCTION 0x04 #define AUTO_ECHO 0x08 #define LOCAL_LOOPBACK 0x10 #define DPLL_NULL 0x00 #define DPLL_ENTER_SEARCH_MODE 0x20 #define DPLL_RESET_MISSING_CLOCK 0x40 #define DPLL_DISABLE_DPLL 0x60 #define DPLL_SOURCE_BRG 0x80 #define DPLL_SOURCE_RTXC 0xA0 #define DPLL_FM_MODE 0xC0 #define DPLL_NRZI_MODE 0xE0 /*******************************************************************/ /* 8530 Read Register 0 */ /*******************************************************************/ #define RX_CHAR_AVAIL 0x01 #define ZERO_COUNT 0x02 #define TX_BUFFER_EMPTY 0x04 #define DCD_STATUS 0x08 #define SYNC_HUNT 0x10 #define CTS_STATUS 0x20 #define TX_UNDERRUN_EOM 0x40 #define BREAK_ABORT 0x80 /*******************************************************************/ /* 8530 Read Register 1 */ /*******************************************************************/ #define ALL_SENT 0x01 #define RESIDUE_CODE_2 0x02 #define RESIDUE_CODE_1 0x04 #define RESIDUE_CODE_0 0x08 #define PARITY_ERROR 0x10 #define RX_OVERRUN_ERROR 0x20 #define CRC_FRAMING_ERROR 0x40 #define END_OF_FRAME 0x80 /*******************************************************************/ /* 8530 Read Register 2 */ /*******************************************************************/ /* This Register returns the Interrupt Status via CH B. */ /*******************************************************************/ /*******************************************************************/ /* 8530 Read Register 3 */ /*******************************************************************/ #define CHB_EXT_STAT_IP 0x01 #define CHB_TX_IP 0x02 #define CHB_RX_IP 0x04 #define CHA_EXT_STAT_IP 0x08 #define CHA_TX_IP 0x10 #define CHA_RX_IP 0x20 /*******************************************************************/ /* 8530 Read Register 10 */ /*******************************************************************/ #define ON_LOOP 0x02 #define LOOP_SENDING 0x10 #define TWO_CLOCKS_MISSING 0x40 #define ONE_CLOCK_MISSING 0x80 /*******************************************************************/ /* 8530 Read Register 12 */ /*******************************************************************/ /* This Register returns the Lower Byte of Time Constant */ /*******************************************************************/ /*******************************************************************/ /* 8530 Read Register 13 */ /*******************************************************************/ /* This Register returns the Upper Byte of Time Constant */ /*******************************************************************/ /*******************************************************************/ /* 8530 Read and Write Register 15 */ /*******************************************************************/ #ifdef Z85230 #ifdef Z85C30 #define WR7P_ACCESS 0x01 #endif #endif #define NO_EXT_STAT_INT 0x00 #define ZERO_COUNT_IE 0x02 #define DCD_IE 0x08 #define SYNC_HUNT_IE 0x10 #define CTS_IE 0x20 #define TX_UNDERRUN_IE 0x40 #define BREAK_ABORT_IE 0x80 /*******************************************************************/ /* End of File */ /*******************************************************************/