AN00001.TXT Advanced Communication Board Developer's Toolkit 1995 ---------------------------------------------------------------------- ---------------------------------------------------------------------- Subject: Direct Memory Access (DMA) Programming information and DMA controller register definitions. Direct Memory Access (DMA) is a method of data transfer that allows information to be transferred from memory to an I/O device, bypassing the CPU. DMA transfers can occur between two memory buffers, from an I/O port to memory, or from memory to an I/O port. DMA is the fastest and most efficient way to transfer data on PC/XT/AT computer. The PC has four DMA channels that service eight bit devices (0-3). On an XT computer, DMA channel 0 is used by the system board for Dynamic Memory Refresh and unavailable to the user. On an AT computer, DMA channel 0 is available. DMA channel 2 is used by the floppy disk controller but may be used when the floppy disk is not in use. When using DMA with an ACB adapter, the first thing that must be set is the DMA jumper options on the card. The Z85x30 can has four programmable pins that can be used to drive DMA circuitry (two for each channel on the SCC). WAIT/REQ and DTR/REQ are the DMA control lines on the SCC and both are available on each channel of the SCC. The following table details DMA request signals that each ACB adapter supports. Signal WAIT/REQ DTR/REQ WAIT/REQ DTR/REQ Ch A Ch A Ch B Ch B Adapter ACB-II X ACB-III X X X ACB-IV X X X ACB-V X X X ACB-VI X X ACB-530 X X X X ACB-104 X X Note: The MAXPORT, ACB-MP, and PC-ACB PCMCIA cards do not support DMA transfers. Please note that the WAIT/REQ (WR1) signal can be programmed to function as a DMA request signal for Transmit OR Receive and DTR/REQ (WR14) can ONLY be programmed to function as a DMA request on Transmit. This setting is important when using full duplex DMA because it requires the use WAIT/REQ for Receive DMA. Please refer to the ACB adapter user manual for correct jumper settings. Note in addition to selecting a DMA channel, a jumper must be set to determine if DMA is enabled always or is enabled by setting a bit in the Control/Status Port on the ACB. Note that enabling DMA at the board level is accomplished differently on some of the ACB adapters. Please refer to the user manual details on DMA enable bit locations. Programming DMA is a very straightforward procedure. Once the basic concept of DMA is grasped, the programming efforts will appear to be very simple. Providing all jumper are set properly, the first step will be to disable the DMA channel being programmed on the DMA Controller. Disabling the DMA channel is done by writing to the Single Channel Mask Register (0A Hex) or by writing to the Mask All Register (0F Hex). When the DMA is disabled at the DMA Controller, program the other DMA registers. The Mode Register, Address Register, Page Register, and the Terminal Count Register must be set. At this point, the Z85x30 SCC will need to be programmed (if the SCC is not already done) in Write Registers 1 and 14. The Mode Register Values will determine what type of DMA transfer will take place (i.e. which DMA channel, I/O to MEM or MEM to I/O, etc.). The Address Register contains the lower 16 bits of the 20 bit physical address of the DMA buffer (Transmit or Receive Buffer). The Page Register will be programmed with the upper 4 bits of the 20 physical address. The Terminal Count Register should be programmed with a value one less than the actual number of bytes to be transferred. When these registers have been set with the proper values, the DMA channel should be enabled by writing to the Single Channel Mask Register or to the Mask All Register. After the DMA channel is enabled, the DMA Transfer will begin. The Terminal Count Value can be read during the DMA transfer. This value will decrement until the count reaches -1 (rolls over from 0 to 65535). When the count equals -1, the DMA transfer is complete. The ACB-530 and the ACB-VI can be set to generate an interrupt, when the Terminal Count (-1) has been reached. When using SDLC, the SCC may be programmed to interrupt on the first character and at End of Frame. These interrupt conditions are often used to notify the application that a DMA transfer needs to be initialized. Direct Memory Access on the PC does have its limitations. The first limitation is speed. Maximum data rates obtainable with DMA are around 1.5 to 2.0 Mbps, however this maximum data rate does depend on several factors. Please refer to the application note "Maximum Data Rates for the ACB cards" for more details on this topic. The second limitation is that the DMA buffer can not reside on a 64K byte boundary, because the DMA Page Register is not physically connected to the DMA Address Register. When calculating the 20 bit address, the application will need to determine if the DMA buffer resides on a 64K boundary, which can be accomplished by comparing the upper four bits of the 20 bit address of the first and last byte of the DMA buffer. If the two sets of bits are not the same, a new or smaller buffer will need to be allocated. This limitation dictates that all eight bit (channels 0-3) DMA transfers can not be greater than 64K bytes. The following is a brief description of the I8237 Direct Memory Access Controller (DMA) register descriptions and I/O locations in the PC/AT I/O address map. For further details on the DMA Controller, please refer to the Intel Micro Controller Data Book or call technical support at the numbers listed in the README.TXT file located in the root directory of this diskette. - DMA Write Register Reference - Port 08 Hex - Command Register: ( bit number ) 7 6 5 4 3 2 1 0 | | | | | | | | | | | | | | | |- 0 memory to memory disable | | | | | | | 1 memory to memory enable | | | | | | | | | | | | | }--- 0 channel 0 address hold disable | | | | | | 1 channel 0 address hold enable | | | | | | | | | | | }----- 0 controller enable | | | | | 1 controller disable | | | | | | | | | }------- 0 normal timing | | | | 1 compressed timing | | | | | | | }--------- 0 fixed priority | | | 1 rotating priority | | | | | }----------- 0 late write selection | | 1 extended write selection | | | }------------- 0 DREQ sense active high | 1 DREQ sense active low | }--------------- 0 DACK sense active low 1 DACK sense active high Port 09 Hex - Request Register: ( bit number ) 7 6 5 4 3 2 1 0 don't care - X X X X X | |_| 00 select channel 0 | |-- 01 select channel 1 | 10 select channel 2 | 11 select channel 3 | }----- 0 reset request bit 1 set request bit Port 0A Hex - Single Bit Mask: ( bit number ) 7 6 5 4 3 2 1 0 don't care - X X X X X | |_| 00 select channel 0 mask bit | |-- 01 select channel 1 mask bit | 10 select channel 2 mask bit | 11 select channel 3 mask bit | }----- 0 clear mask bit 1 set mask bit Port 0B Hex - Mode Register: ( bit number ) 7 6 5 4 3 2 1 0 don't care - X X X X |_| |_| 00 select channel 0 | | | | | |-- 01 select channel 1 | | | | | 10 select channel 2 | | | | | 11 select channel 3 | | | | | | | | | | 00 verify transfer | | | | }------ 01 write transfer (RX) | | | | 10 read transfer (TX) | | | | 11 illegal | | | | | | | }--------- 0 auto-initialization disable | | | 1 auto-initialization enable | | | | | }----------- 0 address increment selected | | 0 address decrement selected |_| |-------------- 00 demand mode selected 01 single mode selected 10 block mode selected 11 cascade mode selected Port 0C Hex - Clear byte pointer flip/flop: Any data written to this port clears the high/low byte pointer. Port 0D Hex - Master Clear: Any data written to this port clears the DMA controller. Port 0E Hex - Clear mask register: Any data written to this port enables all DMA channels. Port 0F Hex - Write All Mask Register ( bit number ) 7 6 5 4 3 2 1 0 don't care - X X X X | | | | | | | }- 0 clear channel 0 mask bit | | | 1 set channel 0 mask bit | | | | | }--- 0 clear channel 1 mask bit | | 1 set channel 1 mask bit | | | }----- 0 clear channel 2 mask bit | 1 set channel 2 mask bit | }------- 0 clear channel 3 mask bit 1 set channel 3 mask bit - DMA Read Register Reference - Port 08 Hex - Status Register: ( bit number ) (T.C. = terminal count) 7 6 5 4 3 2 1 0 | | | | | | | | | | | | | | | }- 1 channel 0 reached T.C. | | | | | | }--- 1 channel 1 reached T.C. | | | | | }----- 1 channel 2 reached T.C. | | | | }------- 1 channel 3 reached T.C. | | | }--------- 1 channel 0 request | | }----------- 1 channel 1 request | }------------- 1 channel 2 request }-------------- 1 channel 3 request DMA PORT REFERENCE CHANNEL REGISTER RD/WT INTERNAL F/F PORT ADDRESS =============================================================================== 0 BASE ADDRESS - LOW BYTE WT 0 0 BASE ADDRESS - HIGH BYTE WT 1 0 CURRENT ADDRESS - LOW BYTE RD 0 0 CURRENT ADDRESS - HIGH BYTE RD 1 0 BASE WORD COUNT - LOW BYTE WT 0 1 BASE WORD COUNT - HIGH BYTE WT 1 1 CURRENT WORD COUNT - LOW BYTE RD 0 1 CURRENT WORD COUNT - HIGH BYTE RD 1 1 -------------------------------------------------------------------------------- 1 BASE ADDRESS - LOW BYTE WT 0 2 BASE ADDRESS - HIGH BYTE WT 1 2 CURRENT ADDRESS - LOW BYTE RD 0 2 CURRENT ADDRESS - HIGH BYTE RD 1 2 BASE WORD COUNT - LOW BYTE WT 0 3 BASE WORD COUNT - HIGH BYTE WT 1 3 CURRENT WORD COUNT - LOW BYTE RD 0 3 CURRENT WORD COUNT - HIGH BYTE RD 1 3 DMA PAGE REGISTER - PORT 83 HEX -------------------------------------------------------------------------------- 2 BASE ADDRESS - LOW BYTE WT 0 4 BASE ADDRESS - HIGH BYTE WT 1 4 CURRENT ADDRESS - LOW BYTE RD 0 4 CURRENT ADDRESS - HIGH BYTE RD 1 4 BASE WORD COUNT - LOW BYTE WT 0 5 BASE WORD COUNT - HIGH BYTE WT 1 5 CURRENT WORD COUNT - LOW BYTE RD 0 5 CURRENT WORD COUNT - HIGH BYTE RD 1 5 DMA PAGE REGISTER - PORT 81 HEX -------------------------------------------------------------------------------- 3 BASE ADDRESS - LOW BYTE WT 0 6 BASE ADDRESS - HIGH BYTE WT 1 6 CURRENT ADDRESS - LOW BYTE RD 0 6 CURRENT ADDRESS - HIGH BYTE RD 1 6 BASE WORD COUNT - LOW BYTE WT 0 7 BASE WORD COUNT - HIGH BYTE WT 1 7 CURRENT WORD COUNT - LOW BYTE RD 0 7 CURRENT WORD COUNT - HIGH BYTE RD 1 7 DMA PAGE REGISTER - PORT 82 HEX