AN00002.TXT	

Advanced Communication Board Developer's Toolkit 1995
    

    ----------------------------------------------------------------------
    ----------------------------------------------------------------------

Subject:  ACB Baud Rates, Clocking, Digital Phase Lock Loop (DPLL) and the
	   Baud Rate Generator.


TRANSMIT CLOCK OUTPUT OPTIONS - ALL ACB CARDS

The 8530 chip can be programmed to echo different clock sources out of the
TRxC (transmit clock) pin.  Some confusion may arise when using the Baud
Rate Generator as the transmit clock source in 16X (asynchronous) clock mode.

- When the TRxC pin is programmed to echo the Baud Rate Generator output, the
  TRxC pin will reflect a 16X clock rate.

- When the TRxC pin is programmed to echo the transmit clock, the TRxC pin
  will reflect a 1X clock rate.

Example:

- SCC programmed for 16X clock mode, Transmit clock = Baud Rate Generator.
- Baud Rate = 9600 baud.

A) TRxC pin programmed for Baud Rate Generator output.
   Control word = XXXXXX10 Binary.

   - TRxC pin echoes 153.6 KHz clock signal.

B) TRxC pin programmed for Transmit Clock output:
   Control word = XXXXXX01 Binary.

   - TRxC pin echoes 9.600 KHz clock signal.


The following reference is for clock mode control words written to WR11 in
the 8530 SCC on the ACB Family of Advanced Communications Cards. All
configurations assume a TTL-compatible signal on the RTxC pin.

1)  Transmit, Receive clocks supplied by two external sources:

    Transmit clock source = TRxC pin <--- External clock (TX)
    Receive clock source  = RTxC pin <--- External clock (RX)
    TRxC pin = Input
    Control word: 00001000B = 08H

2)  Transmit clock supplied externally, Receive clock = Baud Rate Generator:

    Transmit clock source = TRxC pin <--- External clock
    Receive clock source  = Baud Rate Generator
    TRxC pin = Input
    Control word: 01001000B = 48H

3)  Receive clock supplied externally, Transmit clock = Baud Rate Generator:

    Transmit clock source = Baud Rate Generator
    Receive clock source  = RTxC pin <--- External clock
    TRxC pin = Output = TX clock
    Control word: 01001000B = 15H

4)  Transmit, Receive clocks = Baud Rate Generator:

    Transmit clock source = Baud Rate Generator
    Receive clock source  = Baud Rate Generator
    TRxC pin = Output
    Control word: 01010101B = 55H

5)  Transmit, Receive clock = Single external source connected to TRxC pin:

    Transmit clock source = Receive clock source = TRxC pin <--- External clock
    TRxC pin = Input
    Control word: 00101000B = 28H

6)  Transmit, Receive clock = Single external source connected to RTxC pin:

    Transmit clock source = Receive clock source = RTxC pin <--- External clock
    TRxC pin = Input
    Control word: 00000101B = 04H


THE BAUD RATE GENERATOR (BRG)

    The following formula may be used to determine divisor rates for certain
oscillators supplied on the ACB series of communication boards:

BAUD RATE  = [(XTAL in MHz) * (1/(2 * (2 + DIVISOR)))] / CLOCK MODE

The table below illustrates some common values.

					    DIVISOR VALUE (HEX)
       OSCILLATOR	   BAUD RATE	       Clock mode
	 VALUE		    (BPS)	      (X1)    (X16)
    ================================================================
     * 4.9152 MHz	    76.8K	       1E      0
			    38.4K	       3E      2
			    19.2K	       7E      6
			    9600	       FE      0E
			    4800	      1FE      1E
    ================================================================
       4.0   MHz	    1.0M	       0       N/A
			    500K	       2       N/A
			    400K	       3       N/A
			    200K	       8       N/A
			    100K	       12      N/A
    ================================================================
       6.144 MHz	    1.024M	       1       N/A
    ================================================================

* Note:  The standard ACB board configuration uses a 4.9152 MHz oscillator
and a 6 MHz SCC chip.  High baud rate applications may require a faster
oscillator or SCC chip to be supplied on the ACB board.  For further
assistance, please contact the technical support at the numbers listed in
the README.TXT file located in the root directory if this diskette.

ACB Ports


The formula is:		BAUD = 4915200 / (2 x (2 + DIVISOR)).  
			DIVISOR = (( 4915200 / BAUD) / 2 ) - 2  

For 16x async:		BAUD = (4915200 / 16) / (2 x (2 + DIVISOR )).  
			DIVISOR = (( 307200 / BAUD) / 2 ) - 2  


THE DIGITAL PHASE LOCKED LOOP (DPLL)

When using the SCC in synchronous modes, the application may require that
only data (TX and RX) signals be included in the cabling. The SCC will
allow the clocking signals to be encoded in the data stream and recovered by
the receiver. This is accomplished by a phase locked loop. The 85x30 will
support several common formats of clock encoding, including Non-Return to Zero
(NRZ), Non-Return to Zero Inverted (NRZI), FM0, FM1, and Manchester Encoding.
The Digital Phase Locked Loop requires that the oscillator on both the
transmitting and receiving end be able to obtain the same data rates (The
same frequency or multiples of the same frequency).

For further details on data rates and clocking options, please refer to the
SCC User Manual or the application note "Maximum Data Rates for the ACB
cards." If there are any other questions or comments, please contact
technical support at the numbers listed in the README.TXT file located in
the root directory of this diskette.