AN00020.TXT

Advanced Communication Board Developer's Toolkit 1995
    

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Subject: Known problem with Z8530 / Z85230 DPLL and RS-485

Due to the nature of RS-485 communications an idle line condition is present at 
intervals between block transmissions. Transitions from an idle condition to a 
valid data / clock signal can cause problems with the SCC / ESCC clocking 
circuit when the Digital Phase Locked Loop (DPLL) is used to clock the receiver.

To illustrate this problem consider a two wire RS-485 point to point network with
two nodes, 'A' and 'B'. Both nodes are using the DPLL to clock the receiver and 
the clock is encoded in the data stream by the SCC / ESCC encoding features. For 
this example assume SDLC is used for the underlying protocol. Initially neither 
A or B is driving the line so the line is idle (no transitions to decode by the 
DPLL). This will cause the SCC / ESCC DPLL to enter search mode (i.e. looking for
transitions). At some point in time node A will begin to transmit causing the line 
to transition. The transmission will include several SYNC flags (7E hex) preceding
the data to guarantee a valid frame. If the output of the DPLL is viewed from the 
TRXC pin on the receiving SCC / ESCC a glitch in the decoded clock can be viewed 
at the beginning of some of the received frames. This glitch is not present on all
frames, however it causes all data to be shifted by one bit in the receiver, 
causing CRC errors. If the address search feature of the SCC / ESCC is used the 
frames are never passed to the receiver. It appears that the DPLL is adjusting the
output clock with respect to the receiver and an extra bit is inserted.