/********************************************************************* R56_IO.H This header file defines the bit positions of the #5010 R56 Adapter. All declarations are pertainig to the I/O mapped control / status ports on the card. This file also contains function prototypes for C callable functions that access the Z16C32 registers and shared memory range. (C) Copyright Sealevel Systems, Inc., 1995 SEALEVEL SYSTEMS INCORPORATED. 155 Technology Place P.O. Box 830 Liberty, SC 29657 USA (864) 843-4343 (864) 843-3067 FAX ********************************************************************** History: 07-19-95 JGY Original module 10-27-95 JGY Updated for Windows (16 bit support) *********************************************************************/ #ifndef _INC_R56_IO_H // Make sure we are only defined once #define _INC_R56_IO_H /******************************************************************* Run Time Structures *******************************************************************/ typedef struct tagIUSCLINKLISTDMA {DWORD lBufferAddress; /* 32 bit buffer address*/ WORD wByteCount; /* Byte Count */ WORD wCSB; /* Control Status Block */ WORD wCCLength; /* TCC Length, RCC Residueal,*/ WORD wNotUsed; /* Not used */ DWORD lNextAddress; /* Next Buffer or Link Address*/ }IUSCLINKLISTDMA, FAR * fpIUSCLINKLISTDMA; #pragma pack(1) /* Align on Byte boundary */ typedef struct tR56_INFO {LPBYTE MemoryBase; /* MemoryBase */ LPWORD InitArray; /* Address of InitArray */ VOIDINTPROC IUSCISR; fpIUSCLINKLISTDMA TxLinkList; fpIUSCLINKLISTDMA RxLinkList; WORD wIOAddress; /* Base I/O address */ WORD wRedTxFrames; WORD wRedRxFrames; WORD wTotalTxFrames; WORD wTotalRxFrames; WORD wAppTxFrame; WORD wAppRxFrame; WORD wISRTxFrame; WORD wISRRxFrame; WORD wFlags; WORD hCaller; WORD wTxArrayOffset; /* Offset of Tx Link List */ WORD wRxArrayOffset; /* Offset of Rx Link List */ BYTE IOValue1; /* I/O port value at Base+1 */ BYTE IOValue2; /* I/O port value at Base+2 */ BYTE IUSCIRQ; /* IRQ */ BYTE bStatus; /* */ } R56_INFO, DEVICECONTEXT, FAR *fpR56_INFO, FAR *HDEVICE; #pragma pack() /* Revert to default packing */ /******************************************************************* Function Prototypes (card specific) *******************************************************************/ WORD SetR56Interface(fpR56_INFO, BYTE); WORD SetR56Clock(fpR56_INFO, BYTE); WORD VerifyR56(fpR56_INFO ); DWORD ResetIUSC(fpR56_INFO ); WORD InitIUSC(fpR56_INFO ); VOID DisableR56(fpR56_INFO fpCard); VOID ChangeR56Page(fpR56_INFO , BYTE); VOID IUSCoutb(fpR56_INFO , BYTE, BYTE); BYTE IUSCinb(fpR56_INFO , BYTE); VOID IUSCout(fpR56_INFO , BYTE, WORD); WORD IUSCin(fpR56_INFO , BYTE); /******************************************************************* Constants to make init easier. These defines are dependant on the Z16C32 header file (Z16C32.H) *******************************************************************/ #define SELECT_V35 Port3_PinCtrl_Input | Port2_PinCtrl_Output0 #define SELECT_EIA530 Port3_PinCtrl_Input | Port2_PinCtrl_Input #define SELECT_RS232 Port3_PinCtrl_Output0 | Port2_PinCtrl_Output0 #define RTS_ON Port7_PinCtrl_Output1 #define RTS_OFF Port7_PinCtrl_Output0 #define DTR_ON Port6_PinCtrl_Output1 #define DTR_OFF Port6_PinCtrl_Output0 #define CTS_OFF CTS_PinStatus_Zero #define CTS_ON CTS_PinStatus_One #define DCD_OFF DCD_PinStatus_Zero #define DCD_ON DCD_PinStatus_One #define RI_ON TxREQ_PinStatus_One #define RI_ZERO TxREQ_PinStatus_Zero #define DSR_ON RxREQ_PinStatus_One #define DSR_ZERO RxREQ_PinStatus_Zero #define TXC_OUTPUT Port5_PinCtrl_Output0 #define TXC_INPUT Port5_PinCtrl_Output1 #define P0_IS_CLOCK Port0_PinCtrl_CTR0_Clock /******************************************************************* Constants for SetR56Interface and SetR56Clock. *******************************************************************/ #define SET_EIA530 0x01 #define SET_RS232 0x02 #define SET_V35 0x03 #define SET_TXC_INPUT 0x01 #define SET_TXC_OUTPUT 0x02 /******************************************************************* Constants to add to register addresses to control initialization. *******************************************************************/ #define writeH 0x8000 /* write the MS byte */ #define writeL 0x4000 /* write the LS byte */ #define writeW 0x0C000 /* write the whole word */ #define checkH 0x2000 /* read back & check the MB byte */ #define checkL 0x1000 /* read back & check the LS byte */ #define checkW 0x3000 /* read back and check the word */ /******************************************************************* I/O offsets *******************************************************************/ #define R56_0 0x00 #define R56_1 0x01 #define R56_2 0x02 #define R56_3 0x03 /******************************************************************* Return Codes and Error Codes *******************************************************************/ #define ER_BADRESET 0x01 /* Reset always ON */ #define ER_RESETTO 0x02 /* Reset Timed out */ #define ER_BADMEMORY 0x03 /* Bad Memory Range specified */ #define ER_BADIRQ 0x04 /* Bad IRQ specified */ /******************************************************************* Misc Equates *******************************************************************/ #define R56_PAGE_SIZE 0x3fff /* Memory Window Size */ #define ST_TX_STOPPED 0x01 /* Transmitter Stopped */ #define ST_RX_STOPPED 0x02 /* Receiver Stopped */ /******************************************************************* Base+0 Read and Write *******************************************************************/ #define MEM_WIN_ON 0x80 /* Memory Window ON */ #define MEM_WIN_OFF 0x00 /* Memory Window OFF*/ #define IUSC_DISABLE 0x40 /* Disable host access to IUSC registers */ #define IUSC_ENABLE 0x00 /* Enable host access to IUSC registers */ #define MEM_PAGE_0 0x00 /* Memory Window at Page 0 (HIAD=0 Only) */ #define MEM_PAGE_FIRST MEM_PAGE_0 #define MEM_PAGE_1 0x01 /* Memory Window at Page 1 (HIAD=0 Only) */ #define MEM_PAGE_2 0x02 /* Memory Window at Page 2 (HIAD=0 Only) */ #define MEM_PAGE_3 0x03 /* Memory Window at Page 3 (HIAD=0 Only) */ #define MEM_PAGE_4 0x04 /* Memory Window at Page 4 (HIAD=0 Only) */ #define MEM_PAGE_5 0x05 /* Memory Window at Page 5 (HIAD=0 Only) */ #define MEM_PAGE_6 0x06 /* Memory Window at Page 6 (HIAD=0 Only) */ #define MEM_PAGE_7 0x07 /* Memory Window at Page 7 (HIAD=0 Only) */ #define MEM_PAGE_8 0x08 /* Memory Window at Page 8 (HIAD=0 Only) */ #define MEM_PAGE_9 0x09 /* Memory Window at Page 9 (HIAD=0 Only) */ #define MEM_PAGE_A 0x0A /* Memory Window at Page A (HIAD=0 Only) */ #define MEM_PAGE_B 0x0B /* Memory Window at Page B (HIAD=0 Only) */ #define MEM_PAGE_C 0x0C /* Memory Window at Page C (HIAD=0 Only) */ #define MEM_PAGE_D 0x0D /* Memory Window at Page D (HIAD=0 Only) */ #define MEM_PAGE_E 0x0E /* Memory Window at Page E (HIAD=0 Only) */ #define MEM_PAGE_F 0x0F /* Memory Window at Page F (HIAD=0 Only) */ #define MEM_PAGE_LAST MEM_PAGE_F /******************************************************************* Base+1 Write Only *******************************************************************/ #define SEL_IRQ_NONE 0x00 /* No IRQ selected */ #define SEL_IRQ_3 0x20 /* IRQ 3 Selected */ #define SEL_IRQ_4 0x40 /* IRQ 4 Selected */ #define SEL_IRQ_9 0x60 /* IRQ 9 Selected */ #define SEL_IRQ_10 0x80 /* IRQ 10 Selected */ #define SEL_IRQ_11 0x0A0 /* IRQ 11 Selected */ #define SEL_IRQ_12 0x0C0 /* IRQ 12 Selected */ #define SEL_IRQ_15 0x0E0 /* IRQ 15 Selected */ /*Note that the following references are linear notations */ /* i.e. C00K = C00000 */ #define MEM_HI_C00K 0x00 /* High Address C00000-C3FFFF (HIAD=1) */ #define MEM_HI_C40K 0x02 /* High Address C40000-C7FFFF (HIAD=1) */ #define MEM_HI_C80K 0x04 /* High Address C80000-CBFFFF (HIAD=1) */ #define MEM_HI_CC0K 0x06 /* High Address CC0000-CFFFFF (HIAD=1) */ #define MEM_HI_D00K 0x08 /* High Address D00000-D3FFFF (HIAD=1) */ #define MEM_HI_D40K 0x0A /* High Address D40000-D7FFFF (HIAD=1) */ #define MEM_HI_D80K 0x0C /* High Address D80000-DBFFFF (HIAD=1) */ #define MEM_HI_DC0K 0x0E /* High Address DC0000-DFFFFF (HIAD=1) */ #define MEM_HI_E00K 0x10 /* High Address E00000-E3FFFF (HIAD=1) */ #define MEM_HI_E40K 0x12 /* High Address E40000-E7FFFF (HIAD=1) */ #define MEM_HI_E80K 0x14 /* High Address E80000-EBFFFF (HIAD=1) */ #define MEM_HI_EC0K 0x16 /* High Address EC0000-EFFFFF (HIAD=1) */ #define MEM_HI_F00K 0x18 /* High Address F00000-F3FFFF (HIAD=1) */ #define MEM_HI_F40K 0x1A /* High Address F40000-F7FFFF (HIAD=1) */ #define MEM_HI_F80K 0x1C /* High Address F80000-FBFFFF (HIAD=1) */ #define MEM_HI_FC0K 0x1E /* High Address FC0000-FFFFFF (HIAD=1) */ /* Note that the following references are segment notations */ /* i.e. segment 8000 = 80000 linear */ #define MEM_LO_8000 0x00 /* Low Address 80000-83FFF (HIAD=0) */ #define MEM_LO_8400 0x01 /* Low Address 84000-87FFF (HIAD=0) */ #define MEM_LO_8800 0x02 /* Low Address 88000-8BFFF (HIAD=0) */ #define MEM_LO_8C00 0x03 /* Low Address 8C000-8FFFF (HIAD=0) */ #define MEM_LO_9000 0x04 /* Low Address 90000-93FFF (HIAD=0) */ #define MEM_LO_9400 0x05 /* Low Address 94000-97FFF (HIAD=0) */ #define MEM_LO_9800 0x06 /* Low Address 98000-9BFFF (HIAD=0) */ #define MEM_LO_9C00 0x07 /* Low Address 9C000-9FFFF (HIAD=0) */ #define MEM_LO_A000 0x08 /* Low Address A0000-A3FFF (HIAD=0) */ #define MEM_LO_A400 0x09 /* Low Address A4000-A7FFF (HIAD=0) */ #define MEM_LO_A800 0x0A /* Low Address A8000-ABFFF (HIAD=0) */ #define MEM_LO_AC00 0x0B /* Low Address AC000-AFFFF (HIAD=0) */ #define MEM_LO_B000 0x0C /* Low Address B0000-B3FFF (HIAD=0) */ #define MEM_LO_B400 0x0D /* Low Address B4000-B7FFF (HIAD=0) */ #define MEM_LO_B800 0x0E /* Low Address B8000-BBFFF (HIAD=0) */ #define MEM_LO_BC00 0x0F /* Low Address BC000-BFFFF (HIAD=0) */ #define MEM_LO_C000 0x10 /* Low Address C0000-C3FFF (HIAD=0) */ #define MEM_LO_C400 0x11 /* Low Address C4000-C7FFF (HIAD=0) */ #define MEM_LO_C800 0x12 /* Low Address C8000-CBFFF (HIAD=0) */ #define MEM_LO_CC00 0x13 /* Low Address CC000-CFFFF (HIAD=0) */ #define MEM_LO_D000 0x14 /* Low Address D0000-D3FFF (HIAD=0) */ #define MEM_LO_D400 0x15 /* Low Address D4000-D7FFF (HIAD=0) */ #define MEM_LO_D800 0x16 /* Low Address D8000-DBFFF (HIAD=0) */ #define MEM_LO_DC00 0x17 /* Low Address DC000-DFFFF (HIAD=0) */ #define MEM_LO_E000 0x18 /* Low Address E0000-E3FFF (HIAD=0) */ #define MEM_LO_E400 0x19 /* Low Address E4000-E7FFF (HIAD=0) */ #define MEM_LO_E800 0x1A /* Low Address E8000-EBFFF (HIAD=0) */ #define MEM_LO_EC00 0x1B /* Low Address EC000-EFFFF (HIAD=0) */ #define MEM_LO_F000 0x1C /* Low Address F0000-F3FFF (HIAD=0) */ #define MEM_LO_F400 0x1D /* Low Address F4000-F7FFF (HIAD=0) */ #define MEM_LO_F800 0x1E /* Low Address F8000-FBFFF (HIAD=0) */ #define MEM_LO_FC00 0x1F /* Low Address FC000-FFFFF (HIAD=0) */ /******************************************************************* Base+2 Write Only *******************************************************************/ #define HIADD 0x80 /* High Memory Address */ #define LOADD 0x00 /* Low Memory Address */ #define ZERO_WS 0x40 /* Enable zero wait state opperation with RAM*/ #define NO_ZERO_WS 0x00 /* Disable zero wait state opperation with RAM*/ #define EN_16_BIT 0x20 /* Enable 16 bit operations with RAM */ #define ISA_IRQ 0x10 /* Positive Edge IRQ */ #define EISA_IRQ 0x00 /* wire OR low level IRQ (EISA Only) */ /******************************************************************* Base+3 Read *******************************************************************/ #define V35_JUMPER 0x80 /* V.35 Header installed */ #define IRQ_ACTIVE 0x20 /* The 16C32 Interrupt (IRQ) line is active */ #define NOT_RESET 0x10 /* Shows that another write to Base+3 needed*/ #define SLOT_OK 0x08 /* 1 for 16 bit slot, 0 for 8 bit slot */ /******************************************************************* Base+3 Write *******************************************************************/ #define RESET_16C32 0x00 /* Note that ANY value written*/ /* to Base+3 will reset the board. */ #endif // endif for _INC_R56_IO_H define /******************************************************************* End of File *******************************************************************/