/***************************************************************************
****************************************************************************
***
*** Program File: @(#)async33_fifo.v
***
****************************************************************************
****************************************************************************/
//-----------------------------------------------------------------
// (c) copyrights 1993. All rights reserved
// RAVIcad
//
// Company confidential and Proprietary information.
// This information may not be disclosed to unauthorized
// individual.
//-----------------------------------------------------------------
// ***************************
// SCCS file :"async_fifo.v
// Revision :"1.1"
// Mod Date :"95/09/27"
// Mod Time :"14:06:29"
// ***************************
// -------------------------------------------------------------------------
// This module implements the 4 deep async fifo used for staging data between
// the two buses.
// NOTE this fifo has the extra bit for passage of the last flag to the slave
// machine
// 11-29-95 added scan_enable to turn off fifo_rst in order to pass
// test compiler.
//
// ------------------------------------------------------------------------
// deleted parity, not used
module async33_fifo
`ifdef VCS // VCS Release 5.0.1A
`protected
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`endprotected
`endif
endmodule // end of fifo module.
module FIFO_RAM_L
`ifdef VCS // VCS Release 5.0.1A
`protected
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`endif
endmodule
This page: |
Created: | Thu Aug 19 12:02:15 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/pci_core/rtl.vcs/async33_fifo.vp
|