/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)async_fifo.v
***
****************************************************************************
****************************************************************************/
//-----------------------------------------------------------------
//  (c) copyrights 1993. All rights reserved
//      RAVIcad
//
//      Company confidential and Proprietary information.
//      This information may not be disclosed to unauthorized
//      individual.
//-----------------------------------------------------------------
//  ***************************
//   SCCS file :"async_fifo.v
//   Revision  :"1.9"
//   Mod Date  :"95/12/14"
//   Mod Time  :"08:23:48"
// ***************************
// -------------------------------------------------------------------------
//  This module implements the 4 deep async fifo used for staging data between
//  the two buses.
//  11-29-95 added scan_enable to turn off fifo_rst in order to pass
// 		test compiler.
//
//
// ------------------------------------------------------------------------

module async_fifo
`ifdef VCS  // VCS Release 5.0.1A
`protected
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<66+P-\f\CX?-T`endprotected
`endif
endmodule       // end of fifo module.

module FIFO_RAM
`ifdef VCS  // VCS Release 5.0.1A
`protected
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`endprotected
`endif
endmodule