/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 
`define CYCLETIME 20
`define VCS
`define A24_STUB 1
`define FPU_PRESENT 1
`define IU_RTL 1
`define RTL_TLB 1
`define Mdecode Msystem.ssparc.ssparc_core.iu.iuchip.decode
`define Mexec Msystem.ssparc.ssparc_core.iu.iuchip.exec
`define Mhold_control Msystem.ssparc.ssparc_core.iu.iuchip.hold_control
`define Mpc Msystem.ssparc.ssparc_core.iu.iuchip.pc
`define Mqueue Msystem.ssparc.ssparc_core.iu.iuchip.queue
`define Mregfile Msystem.ssparc.ssparc_core.iu.iuchip.regfile
`define botpads Msystem.ssparc.ssparc_iopads.botpads
`define clkbuf_c Msystem.ssparc.clkbuf_c
`define dp_mmu Msystem.ssparc.ssparc_core.ssparc_mmu.MMU_dp
`define fp_ctl Msystem.ssparc.ssparc_core.ssparc_fpu.fpctl
`define fp_exp Msystem.ssparc.ssparc_core.ssparc_fpu.fpexp
`define fp_fpc Msystem.ssparc.ssparc_core.ssparc_fpu.fpfpc
`define fp_fpm Msystem.ssparc.ssparc_core.ssparc_fpu.fpfpm
`define fp_frac Msystem.ssparc.ssparc_core.ssparc_fpu.fpfrac
`define fp_rf Msystem.ssparc.ssparc_core.ssparc_fpu.fprf
`define fp_rom Msystem.ssparc.ssparc_core.ssparc_fpu.fprom
`define leftpads Msystem.ssparc.ssparc_iopads.leftpads
`define m_mmu_cntl Msystem.ssparc.ssparc_core.ssparc_mmu.MMU_cntl
`define mc_d_tag_cache Msystem.ssparc.ssparc_core.caches.d_tag_cache
`define mc_i_tag_cache Msystem.ssparc.ssparc_core.caches.i_tag_cache
`define mc_tlb Msystem.ssparc.ssparc_core.ssparc_mmu.MMU_tlb
`define misc Msystem.ssparc.clk_misc.ssparc_misc
`define pll Msystem.ssparc.pll
`define rightpads Msystem.ssparc.ssparc_iopads.rightpads
`define rl_clk_cntl Msystem.ssparc.clk_misc.clk_cntl
`define rl_dc_cntl Msystem.ssparc.ssparc_core.cc.dc_cntl
`define rl_ic_cntl Msystem.ssparc.ssparc_core.cc.ic_cntl
`define rl_jtag_cntl Msystem.ssparc.clk_misc.jtag_cntl
`define rl_memif Msystem.ssparc.ssparc_core.ssparc_memif
`define sbc Msystem.ssparc.ssparc_core.ssparc_sbc
`define ssparc_core Msystem.ssparc
`define SSPARC_CORE Msystem.ssparc.ssparc_core
`define toppads Msystem.ssparc.ssparc_iopads.toppads
`define SS_SCOPE Msystem.ssparc
`define CLK_CNTL Msystem.ssparc.clk_misc.clk_cntl
`define IU Msystem.ssparc.ssparc_core.iu
`define FPU Msystem.ssparc.ssparc_core.ssparc_fpu
`define FPUREG Msystem.ssparc.ssparc_core.ssparc_fpu.fprf
`define DCACHE Msystem.ssparc.ssparc_core.caches.d_tag_cache.dcache_data.dram.dc_ram
`define DTAG Msystem.ssparc.ssparc_core.caches.d_tag_cache.dcache_tag.dtram.t_ram
`define DTAGV Msystem.ssparc.ssparc_core.caches.d_tag_cache.dcache_tag.dtram.t_v_ram
`define DTAGC Msystem.ssparc.ssparc_core.caches.d_tag_cache.dcache_tag.dtram.t_cntx_ram
`define DTAGA Msystem.ssparc.ssparc_core.caches.d_tag_cache.dcache_tag.dtram.t_acc_ram
`define ICACHE Msystem.ssparc.ssparc_core.caches.i_tag_cache.icache_data.iram.ic_ram
`define ITAG Msystem.ssparc.ssparc_core.caches.i_tag_cache.icache_tag.itram.t_ram
`define ITAGV Msystem.ssparc.ssparc_core.caches.i_tag_cache.icache_tag.itram.t_v_ram
`define ITAGC Msystem.ssparc.ssparc_core.caches.i_tag_cache.icache_tag.itram.t_cntx_ram
`define ITAGA Msystem.ssparc.ssparc_core.caches.i_tag_cache.icache_tag.itram.t_acc_ram
`define log2_icachesize 14
`define log2_dcachesize 13
`define log2_iblksize 5
`define log2_dblksize 4
`define DCACHE_CNTL Msystem.ssparc.ssparc_core.cc.dc_cntl
`define ICACHE_CNTL Msystem.ssparc.ssparc_core.cc.ic_cntl
`define log2_main_mem_size 28
`define MMU Msystem.ssparc.ssparc_core.ssparc_mmu
`define MMU_DPATH Msystem.ssparc.ssparc_core.ssparc_mmu.MMU_dp
`define MMU_CNTL Msystem.ssparc.ssparc_core.ssparc_mmu.MMU_cntl
`define MISC Msystem.ssparc.clk_misc.ssparc_misc
`define BOARD Msystem
`define rst `BOARD.reset
`define SSCANPATH "/tmp/"
`define INITIAL_PCR 
`define TOPDIR "512_zeros"
`define TCK_START 3

`timescale      1ns / 1ns