/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/* This file contains basic parameters required by the Singlesparc
chip to define the cache & tag. Primary parameters are used
to derive secondary terms.
*/
// Primary parameters (all in bytes unless indicated)
`define ifillcnt 4 /* Icache fill count in double-words */
`define ifillcntmsb 3 /* Icache fill count MSB */
`define dfillcnt 2 /* Dcache fill count in double-words */
`define log2_maxphysize 27 /* max 128Mbyte physical address */
`define mspa (`log2_maxphysize-1) /* MSB of physical addresses */
`define log2_datasize 3 /* 8 bytes = data width (word - 32 bits) */
`define log2_pagesize 12 /* 4Kbytes is page size */
`define log2_pagesize_msb (`log2_pagesize-1) /* MSB of page size */
// main memory stuff
// log2_main_mem_size is a dynamic parameter, defined by the run script.
`define main_mem_size (1<<`log2_main_mem_size) /* main_mem size in bytes */
// Secondary parameters
// icache data
`define ic_msb (`log2_icachesize-1) /* msb of icache address bit */
`define ic_size (1<<`log2_icachesize) /* icache size in bytes */
`define ic_maxbyte (`ic_size-1) /* icache size msb of no. of bytes */
`define ic_blksize (1<<`log2_iblksize) /* icache blk size in bytes */
`define ic_iblkmsb (`log2_iblksize-1) /* icache blk size MSB */
`define ic_msbwordaddr ((`log2_iblksize-`log2_datasize)-1) /* ic word addr */
// dcache data
`define dc_msb (`log2_dcachesize-1) /* msb of dcache address bit */
// Dcache crtl gets all of these DVA bits, since VA bits within the page
// index are used for PA in small caches.
`define dc_dva_msb ((`log2_dcachesize<`log2_pagesize)?`log2_pagesize_msb:`dc_msb)
`define dc_size (1<<`log2_dcachesize) /* dcache size in bytes */
`define dc_maxbyte (`dc_size-1) /* dcache size msb of no. of bytes */
`define dc_blksize (1<<`log2_dblksize) /* dcache blk size in bytes */
`define dc_msbwordaddr ((`log2_dblksize-`log2_datasize)-1) /* dc word addr */
`define dc_dblksize_msb (`log2_dblksize-1) /* dcache block size MSB */
// tag array (note: assumes direct mapped caches & valid bit is separate)
// itag array
`define it_lspa `log2_icachesize // Vestigial - must remove
`define it_width (31-`log2_icachesize+1) /* width of itag VA field */
`define it_msb (`it_width-1) /* msb of itag VA field */
`define it_blks (`ic_size/`ic_blksize) /* no. of blks in icache */
`define it_maxblks (`it_blks-1) /* msb of blks */
`define it_blkaddr (`log2_icachesize-`log2_iblksize) /* blk addr for itag */
`define it_msbblks ((`log2_icachesize-`log2_iblksize)-1) /* msb of blk addr for itag */
// dtag array
`define dt_lspa `log2_dcachesize // Vestigial - must remove
`define dt_lspa_msb (`dt_lspa - 1) // Vestigial - must remove
`define dt_width (31-`log2_dcachesize+1) /* width of dtag data */
`define dt_msb (`dt_width-1)
`define dt_blks (`dc_size/`dc_blksize) /* no. of blks in dtag */
`define dt_maxblks (`dt_blks-1) /* msb of blks */
`define dt_blkaddr (`log2_dcachesize-`log2_dblksize) /* blk addr for dtag */
`define dt_msbblks ((`log2_dcachesize-`log2_dblksize)-1) /* msb of blk addr for dtag */
This page: |
Created: | Thu Aug 19 12:02:32 1999 |
| From: |
../../../sparc_v8/system/rtl/memdef.h
|