/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
// @(#)defines.v 1.31 3/19/93
/****************************************************************************
* defines.v
*
* Description:
* all the defines for Memory subblock (MCB, DPC, RFR) are made
* here. This file must allways accompany other .v & .vpp files
* for synopsys or verilog.
*
*
* Registered: march 25, 1992
*
* Dependencies:
*
*
*
*
****************************************************************************/
/*############################################################################
*########################## MCB related defines #############################
*###################--------- mcb.v file ------------########################
*############################################################################
*/
/* Define MMU requests.*/
/* -------------------- */
`define MM_ISS (( mm_issue_req == 1'b1 ) && ~(mm_fb_req == 1'b1))
`define G_ISS (( mm_issue_req == 1'b1 ) && (mm_fb_req == 1'b1))
//`define MM_NOP ( mm_mreq[3:0]==4'h0 ) /* No requests*/
`define MM_RD8 ( mm_mreq[3:0]==4'h1 ) /* 8byte (dword) read.*/
`define MM_RD16 ( mm_mreq[3:0]==4'h2 ) /* 16byte Rd (DC & SBus)*/
`define MM_RD32 ( mm_mreq[3:0]==4'h4 ) /* 32byte Rd (IC & SBus)*/
`define MM_WR1 ( mm_mreq[3:0]==4'h9 ) /* byte Wr.*/
`define MM_WR2 ( mm_mreq[3:0]==4'ha ) /* 2Byte (hword) Wr.*/
`define MM_WR4 ( mm_mreq[3:0]==4'hb ) /* 4byte (word) Wr.*/
`define MM_WR8 ( mm_mreq[3:0]==4'hc ) /* 8byte (dword) Wr.*/
`define MM_WR16 ( mm_mreq[3:0]==4'hd ) /* 16byte (quad-word) Wr.*/
`define MM_WAIT ( mm_mreq[3:0]==4'h0 ) /* Release int. data bus.*/
`define MM_RDX ( mm_mreq[3]==1'b0)
//`define MM_REQ ((`MM_ISS) && (mm_mreq[3:0] != 4'h0))
`define MM_REQ (`MM_ISS)
`define MM_REQ2 (( mm_issue_req2 == 1'b1 ) && ~(mm_fb_req == 1'b1))
`define G_REQ (`G_ISS)
`define G_REQ2 (( mm_issue_req2 == 1'b1 ) && (mm_fb_req == 1'b1))
/* Define RFR request.*/
/* --------------------*/
`define RF_REQ ((rf_rreq_l == 1'b0) & ~( mm_issue_req_early == 1'b1 ))
`define SREF_REQ ((mm_rf_cntl_3 == 1'b1) & ~( mm_issue_req_early == 1'b1 ))
/* Define PRECHARGE-EARLY request.*/
//`define PRECHARGE 1'b0
/* Define Level-1 (major) states. (L1)*/
/* ===================================*/
`define STATE fnc_mcb_sm[]
`define L1_RESET 9'h000 /* Init everything.*/
`define L1_WAIT 9'h001 /* Wait for 200us RAM init timeout*/
`define L1_CBR 9'h002 /* Start 8 CbR cycles for RAM init.*/
`define L1_IDLE 9'h080 /* Waiting for a request*/
`define L1_CHECK 9'h081 /* Check for late MMU reqs*/
/* Define Level-2 (secondary) states. (L2)*/
/* =======================================*/
`define L2_CYCEND 9'h003
/* Define Level-3 states. (L3)*/
/* ============================*/
`define L3_CBR01 9'h008 /* Cas before RAS cycles.*/
`define L3_CBR02 9'h009
`define L3_CBR03 9'h00a
`define L3_CBR04 9'h00b
`define L3_CBR05 9'h00c
`define L3_CBR06 9'h00d
`define L3_CBR07 9'h00e
`define L3_SRF01 9'h051
`define L3_RDP01 9'h041 /* Read page or end of non-p0age */
`define L3_RDP01T 9'h045
//`define L3_RDP01U 8'h061 /* for 85 MHZ */
`define L3_RDP02A 9'h010
`define L3_RDP02B 9'h011
`define L3_RDM01 9'h021 /* Read multiple longwords (16 0r 32) */
`define L3_RDM02 9'h022
`define L3_RDM03 9'h023
`define L3_RDM03T 9'h046
//`define L3_RDM03U 9'h062
`define L3_RDM04 9'h024
`define L3_RDM05 9'h025
`define L3_RDM06 9'h026
`define L3_RDM06T 9'h047
//`define L3_RDM06U 9'h063
`define L3_RDM07 9'h027
`define L3_RDM08 9'h028
`define L3_RDM09 9'h029
`define L3_RDM09T 9'h048
//`define L3_RDM09U 9'h064
`define L3_RDP01S 9'h070
`define L3_RDP01SX 9'h071 // YS
`define L3_RAS01 9'h042 /* RAS precharge and RAS, WE and CAS asserts */
// Add state for RAS_l precharge
`define L3_RAS01X 9'h044 /* extra RAS precharge and RAS, WE and CAS asserts */
`define L3_RAS02 9'h02a
`define L3_RAS02X 9'h04b
`define L3_RAS03 9'h02b
`define L3_RAS03X 9'h02e // YS
`define L3_RAS04 9'h02c
//`define L3_RAS04X 9'h04a
//`define L3_RAS04Y 9'h060
`define L3_RAS05 9'h02d
//`define L3_RAS06 9'h02e
`define L3_WRP01 9'h043
`define L3_WRP02 9'h012
`define L3_WRP02W 9'h017
`define L3_WRP03A 9'h013
`define L3_WRP03B 9'h014
`define L3_WRP03C 9'h04c
`define L3_WRP04 9'h04d
`define L3_WRP05 9'h04e
`define L3_WRP06 9'h04f
`define L3_RMWP01 9'h015
`define L3_RMWP02 9'h016
`define L3_RMWP02X 9'h049
//define graphic states starting 90
`define L3_SYNC 9'h090
`define L3_GRDT1 9'h091
`define L3_GRDT2 9'h092
`define L3_GRDT3 9'h093
`define L3_GRDT4 9'h094
`define L3_GRDT5 9'h095
`define L3_GRDT6 9'h096
`define L3_GRDT7 9'h097
`define L3_GRDT8 9'h098
`define L3_GRDT9 9'h099
`define L3_GRDTA 9'h09a
`define L3_GRDTB 9'h09b
`define L3_GRDTC 9'h0b1
`define L3_GRDTD 9'h0b2
`define L3_GRDTE 9'h0b3
`define L3_GRDTF 9'h0b4
`define L3_GRDTG 9'h0b5
`define L3_GRDTH 9'h0b6
`define L3_GRDTI 9'h0b7
`define L3_GRDTJ 9'h0b8
`define L3_GRDTK 9'h0b9
`define L3_GRDTL 9'h0ba
`define L3_GRDTM 9'h0bb
`define L3_GRDTN 9'h0bc
`define L3_GWRT1 9'h0a1
`define L3_GWRT2 9'h0a2
`define L3_GWRT3 9'h0a3
`define L3_GWRT4 9'h0a4
`define L3_GWRT5 9'h0a5
`define L3_GWRT6 9'h0a6
`define L3_GWRT7 9'h0a7
`define L3_GWRT8 9'h0a8
`define L3_GROT3 9'h0ab
`define L3_GHIT1 9'h0ac
`define L3_GHIT2 9'h0ad
// states for cyc_end
`define L3_GRDTX 9'h0c1
`define L3_GWRTB 9'h0c2
/*
define L3_GWRTC 9'h0c3
define L3_GWRTD 9'h0c4
define L3_GWRTE 9'h0c5
define L3_GWRTF 9'h0c6
define L3_GWRTG 9'h0c7
define L3_GWRTH 9'h0c8
*/
/* change decode to make read and write have cyc_type[5:4] fixed for late read size.*/
/* Define cycle types stored in cyc_reg*/
/* ======================================*/
`define CBR 7'h10 /* Cas before Ras refresh cycle*/
`define DRD32N 7'h02 /* Non-Paged 32byte DRAM Rd (4 accesses)*/
`define DRD32P 7'h03 /* Paged 32byte DRAM Rd (4 accesses)*/
`define DRD16N 7'h04 /* Non-Paged 16byte DRAM Rd (2 accesses)*/
`define DRD16P 7'h05 /* Paged 16byte DRAM Rd (2 accesses)*/
`define DRD8N 7'h06 /* Non-Paged 8byte DRAM Rd*/
`define DRD8P 7'h07 /* Paged 8byte DRAM Rd*/
`define DRMW2N 7'h18 /* Non-Paged 2byte DRAM Wr (Rd followed by Wr)*/
`define DRMW2P 7'h19 /* Paged 2byte DRAM Wr (Rd followed by Wr)*/
`define DRMW1N 7'h1a /* Non-Paged 1byte DRAM Wr (Rd followed by Wr)*/
`define DRMW1P 7'h1b /* Paged 1byte DRAM Wr (Rd followed by Wr)*/
`define DWR8N 7'h1c /* Non-Paged 8byte DRAM Wr*/
`define DWR8P 7'h1d /* Paged 8byte DRAM Wr*/
`define DWR4N 7'h1e /* Non-Paged 4byte DRAM Wr*/
`define DWR4P 7'h17 /* Paged 4byte DRAM Wr*/
`define DWR16N 7'h11 /* Non-Paged 16byte DRAM Wr*/
`define DWR16P 7'h12 /* Paged 16byte DRAM Wr*/
`define SREF 7'h13 /* self-refresh cycle */
`define NONE 7'h1f /* NO CYCLES.. In L2_CHECK or L1_??? */
/* following definition is changed for timing reason. */
`define GRD8P 7'h20 /* Paged 8byte graphics Rd*/
`define GRD16P 7'h23 /* Paged 16byte graphics Rd*/
`define GRD32P 7'h26 /* Paged 32byte graphics Rd*/
`define GRDPX (cyc_reg[5:3]==3'b100) /* Paged anybyte graphics Rd*/
`define GRDPXT (cyctype[5:3]==3'b100) /* Paged anybyte graphics Rd*/
`define GRD8H 7'h28 /* update hi-row 8byte graphics Rd*/
`define GRD16H 7'h2b /* update hi-row 16byte graphics Rd*/
`define GRD32H 7'h2e /* update hi-row 32byte graphics Rd*/
`define GRDHX (cyc_reg[5:3]==3'b101)/*non Paged anybyte graphics Rd*/
`define GRDHXT (cyctype[5:3]==3'b101)/*non Paged anybyte graphics Rd*/
//`define GRD8P 7'h20 /* Paged 8byte graphics Rd*/
//`define GRD8H 7'h22 /* update hi-row 8byte graphics Rd*/
//`define GRD16P 7'h23 /* Paged 16byte graphics Rd*/
//`define GRD16H 7'h25 /* update hi-row 16byte graphics Rd*/
//`define GRD32P 7'h26 /* Paged 32byte graphics Rd*/
//`define GRD32H 7'h28 /* update hi-row 32byte graphics Rd*/
/* following definition is changed for timing reason. */
`define GWR8P 7'h30 /* Paged 8byte graphics WR*/
`define GWR4P 7'h36 /* Paged 4byte graphics WR*/
`define GWR2P 7'h34 /* Paged 2byte graphics WR*/
`define GWR1P 7'h35 /* Paged 1byte graphics WR*/
`define GWR16P 7'h33 /* Paged 16byte graphics WR*/
`define GWRPX (cyc_reg[5:3]==3'b110) /* Paged anybyte graphics WR*/
`define GWR8H 7'h38 /* update hi-row 8byte graphics WR*/
`define GWR4H 7'h3e /* update hi-row 4byte graphics WR*/
`define GWR2H 7'h3c /* update hi-row 2byte graphics WR*/
`define GWR1H 7'h3d /* update hi-row 1byte graphics WR*/
`define GWR16H 7'h3b /* update hi-row 16byte graphics WR*/
`define GWRHX (cyc_reg[5:3]==3'b111) /* n-Paged anybyte graphics WR*/
//`define GWR8P 7'h30 /* Paged 8byte graphics WR*/
//`define GWR8H 7'h32 /* update hi-row 8byte graphics WR*/
//`define GWR4P 7'h36 /* Paged 4byte graphics WR*/
//`define GWR4H 7'h38 /* update hi-row 4byte graphics WR*/
//`define GWR2P 7'h39 /* Paged 2byte graphics WR*/
//`define GWR2H 7'h3b /* update hi-row 2byte graphics WR*/
//`define GWR1P 7'h3c /* Paged 1byte graphics WR*/
//`define GWR1H 7'h3e /* update hi-row 1byte graphics WR*/
//`define GWR16P 7'h33 /* Paged 16byte graphics WR*/
//`define GWR16H 7'h35 /* update hi-row 16byte graphics WR*/
/* Miscl defines for commonly used stuff */
/* ========================================*/
`define IS_PAGE (is_page == 1'b1)
`define G_PAGE (mm_fb_page == 1'b1)
`define NO_PAGE (is_page == 1'b0)
`define NG_PAGE (~`G_PAGE)
`define UPDATE_HI (~`G_PAGE )
/*############################################################################
*########################## DPC related defines #############################
*###################--------- dpc.v file ------------########################
*############################################################################
*/
`define WR_RMW ( mc_dpct[5] == 1'b0 )
`define RD ( mc_dpct[5] == 1'b1 )
`define BYTE ( mc_dpct[4:3] == 2'b00 )
`define HWORD ( mc_dpct[4:3] == 2'b01 )
`define WRD_DWRD ( mc_dpct[4] == 1'b1 )
`define DWORD ( mc_dpct[4:3] == 2'b3 )
`define HI32 ( mc_dpct[2] == 1'b0 )
`define LO32 ( mc_dpct[2] == 1'b1 )
`define PA0 mc_dpct[0]
`define PA1 mc_dpct[1]
/*############################################################################
*########################## DRAM related defines #############################
*###################--------- dram.v file ------------########################
*###########################################################################*/
/*
`define Index_Size 100 //Size of the index array for DRAM model in dram_index.v file.
`define CBR_REF 4'b0000
`define READ 4'b0001
`define WRITE 4'b0010
`define NOCAS 4'b1111
`define NORAS 8'b11111111
`define ASSERTED 1
`define NEGATED 0
`define YES 1
`define NO 0
*/
/*############################################################################
*########################## Debug Env. #######################################
*################------------ mem.v --------------############################
*############################################################################*/
`define Msystem Msystem
`define reset `Msystem.reset
`define sys_clk `Msystem.SYS_CLK
/*********************************************************/
`define Mclocks Mclocks
`define cycle_count `Mclocks.cycle_count
`define reset_in `Mclocks.RESET_IN
/*********************************************************/
//`define SSPARC `Msystem.ssparc
//`define mclk `SSPARC.clock
`define mm_caddr `SSPARC_CORE.mm_caddr
`define mm_issue_req `SSPARC_CORE.mm_issue_req
`define mm_iss_req_early `SSPARC_CORE.mm_issue_req_early
//`define mm_mreq `SSPARC.ssparc_memif.mm_mreq
// IIe note : Moved the definitions to mem.v
// put the mm_mreq back for now 5-1-96 JP
// `ifdef MEMIF_GATE_LEVEL
// `define mm_mreq `SSPARC.memif_major.mm_mreq
// `define mm_rf_cntl `SSPARC.memif_major.mm_rf_cntl
// `else
`define mm_mreq `SSPARC_CORE.ssparc_memif.mm_mreq
`define mm_rf_cntl `SSPARC_CORE.ssparc_memif.mm_rf_cntl
// `endif
/*`define mm_rf_cntl `SSPARC.ssparc_memif.mm_rf_cntl */
/*********************************************************/
/* commented out by NeilOS due to conflict with MEM defined in opcode.h */
/* `define MEM `SSPARC_CORE.ssparc_memif.memif_major.mcb.mem */
/*********************************************************/
`define RFR `SSPARC_CORE.ssparc_memif.memif_major.rfr
//OUTPUTS
//`define rf_rreq_l `RFR.rf_rreq_l
/****************************************************************************/
// These definitions specify the type of bus request by Falcon.
`define AFX_REQ (mm_afx_req == 1'b1)
`define AFX_WR8 ((mm_afx_req == 1'b1) && (mm_afx_read == 1'b0))
`define AFX_RD8 ((mm_afx_req == 1'b1) && (mm_afx_read == 1'b1))
// The cycle type register is now 7 bits, with the 7th
// bit defines a Falcon requested cycle.
`define FDRD8N 7'h46 // Non-page 8 byte DRAM read.
`define FDRD8P 7'h47 // Page 8 byte DRAM read.
`define FDWR8N 7'h5c // Non-page 8 byte DRAM write.
`define FDWR8P 7'h5d // Page 8 byte DRAM write.
// Define Level-3 states (L3) exclusive for the AFX master cycles.
// Theses states are synchronized with the g_clk.
// The 9th bit defines AFX master cycles.
`define L3_G_SYNC 9'h181 // Once the IIe grant the bus to Falcon, the
// MCB state machine moves to this state the
// synchronic with g_clk.
`define L3_G_RAS01 9'h142 // RAS precharge and RAS, WE and CAS asserts
`define L3_G_RAS01X 9'h144 // extra RAS precharge and RAS, WE and CAS asserts
`define L3_G_RAS01XX 9'h145 // extra RAS precharge and RAS, WE and CAS asserts YS.
`define L3_G_RAS02 9'h12a
`define L3_G_RAS03 9'h12b
`define L3_G_RAS03X 9'h153 // Last RAS cycle for DRAM read.
`define L3_G_RAS04 9'h12c // Last RAS cycle for DRAM write.
`define L3_G_RAS05 9'h12d // Last RAS cycle for DRAM read.
// at 125MHz.
// Falcon read cycle states.
`define L3_G_RDP01 9'h141 // Read page or end of non-page read.
`define L3_G_RDP02A 9'h110
`define L3_G_RDP02B 9'h111
`define L3_G_CAS175 9'h120
`define L3_G_RDP175 9'h109
`define L3_G_RDM01 9'h121
`define L3_G_RDM02 9'h122
`define L3_G_RDM03 9'h123
`define L3_G_RDM04 9'h124
`define L3_G_RDM05 9'h125
`define L3_G_RDM06 9'h126
`define L3_G_RDM07 9'h127
`define L3_G_RDM08 9'h128
`define L3_G_RDM09 9'h129
`define L3_G_WAIT1 9'h130
`define L3_G_WAIT2 9'h131
This page: |
Created: | Thu Aug 19 12:00:13 1999 |
| From: |
../../../sparc_v8/system/rtl/memif_defs.h
|