/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)pre_sync1.v
***
****************************************************************************
****************************************************************************/
// -----------------------------------------------------------------------------
//
//    COPYRIGHT (C) 1995 BY RAVIcad, Inc.
//    ALL RIGHTS RESERVED
//    PROPRIETARY AND TRADE SECRET
//    USAGE AND DISCLOSURE AS PER LICENSE AGREEMENT.
//
// ----------------------------------------------------------------------------
//  @(#)pre_sync1.v	1.1 10/17/95  
/*  =================================================================
    this module locks incoming signal until resync'd signal clears 
    ================================================================= */

module pre_sync1
`ifdef VCS  // VCS Release 5.0.1A
`protected
++1cVP,,GTgQE04\[O>^NF25e-TJ5cF8[/_.CL:1fK>ffe^]0RVG9?+(KU(3K02=VK#&DO._9=V
L:I#,CQaGIF&\LZ6^V68IU\gJd8E8HY0O#D=9=OX>Y(d6a;.KXF][cW;.\E4#T-6K<9LF9RNG)^eNb)>:WPM>P6J6A8,TDB/
ID+WX/F4L=;b(\KA6A0+_1D&7K3KAGWHb:\EQg-Wff@ROF-\:OcSN2U9A283_X/G
K5@[_U\?,Q8/^\.fTfQ#U-?]6/Q8V<:7TDLHEE\@Y0He,7MLeNG;E,]IMPHK4B;Y
;_8g8fFX^X(5VR#0PR&5SJWL>M=FO/IYN:AG]c5SU_3eH$
`endprotected
`endif
endmodule