/***************************************************************************
****************************************************************************
***
*** Program File: @(#)sync9.v
***
***
****************************************************************************
****************************************************************************/
// -----------------------------------------------------------------------------
//
// COPYRIGHT (C) 1995 BY RAVIcad, Inc.
// ALL RIGHTS RESERVED
// PROPRIETARY AND TRADE SECRET
// USAGE AND DISCLOSURE AS PER LICENSE AGREEMENT.
//
// ----------------------------------------------------------------------------
//
// @(#)sync9.v 1.2 10/16/95
/* =================================================================
this module synchronizes 9 signals from one clk domain to the other
================================================================= */
module sync9
`ifdef VCS // VCS Release 5.0.1A
`protected
L[fDW9M<8WaTO,:E5NLYA6-.-_c3KE5FQSb2Q#P57T[[:aNU/5.EbUXU3Q7).;M75U9)F12JTDbU
5?.)=JBHUU#BYg/+R]fKVY](Y
D5LQLIBe2C/C6.?^L8d&N1>ZeeLfSY_92QI]H?dVCAHG1gRIM+PW_F&a_<:X@>Ug
a5(a##A4D0A5/NER^4#&:8N/G9UQ];UATOKVR#-V7:^ERfSAS_;M/5A/-SIaTY9#
UbK-0E+&T1:f@,(W88Y,._N1TPHRKU8+]ea_cb)E@-D;L56gPUJ--
2:+3)[PZJQ4e--5U#URQ<>C)638QJKf1^QKS4(a?>KPH8bSWXO3><31Q(2LcON##
G\.WOA4R^JHc[2?S/?;AG_ScLCS:g007dIS,9a?6DP,I5]-/f?T?e\\6aTc;C+9T
QLD11g+62N6c,$
`endprotected
`endif
endmodule
This page: |
Created: | Thu Aug 19 11:59:15 1999 |
| From: |
../../../sparc_v8/ssparc/pcic/pci_core/rtl.vcs/sync9.vp
|