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/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)sync_reset.v
***
****************************************************************************
****************************************************************************/
// -----------------------------------------------------------------------------
//
//    COPYRIGHT (C) 1995 BY RAVIcad, Inc.
//    ALL RIGHTS RESERVED
//    PROPRIETARY AND TRADE SECRET
//    USAGE AND DISCLOSURE AS PER LICENSE AGREEMENT.
//
// ----------------------------------------------------------------------------
// 
// @(#)sync_reset.v	1.1 10/16/95
 
/*  =================================================================
    this module psuedo-synchronizes reset line to given clk 
    ================================================================= */

module sync_reset
`ifdef VCS  // VCS Release 5.0.1A
`protected
\fL/3KEcc>S#;((5<>1L9bE3#UX-\-I>_N7/19Z=]b;+-E&G2_L:TJ29V@6df#HK?
(:Y]\aU,f=F+ff=aSW\HW>F(gYW>33X&H_/(IO@Z;C=AS3G<9JZ\+c@0eIRBV4Q=)L@S9DF/(\?Pc
?C([cV2[aV88F6e4Re/bY:MN8N4FPXcJdU1:FQeGeVO8A#1Sf;BG;I:/A]a=^a2g
QPeQ60N47/KPFG;W/I9\B=W6Mf+H@/;M)L7+OaG)AV58H$
`endprotected
`endif
endmodule
   
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This page: Created:Thu Aug 19 12:03:10 1999
From: ../../../sparc_v8/ssparc/pcic/pci_core/rtl.vcs/sync_reset.vp

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