/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
/* The contents of this file are subject to the current version of the Sun    */ 
/* Community Source License, microSPARCII ("the License"). You may not use    */ 
/* this file except in compliance with the License.  You may obtain a copy    */ 
/* of the License by searching for "Sun Community Source License" on the      */ 
/* World Wide Web at http://www.sun.com. See the License for the rights,      */ 
/* obligations, and limitations governing use of the contents of this file.   */ 
/*                                                                            */ 
/* Sun Microsystems, Inc. has intellectual property rights relating to the    */ 
/* technology embodied in these files. In particular, and without limitation, */ 
/* these intellectual property rights may include one or more U.S. patents,   */ 
/* foreign patents, or pending applications.                                  */ 
/*                                                                            */ 
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos,   */ 
/* Solaris, Java and all Java-based trademarks and logos are trademarks or    */ 
/* registered trademarks of Sun Microsystems, Inc. in the United States and   */ 
/* other countries. microSPARC is a trademark or registered trademark of      */ 
/* SPARC International, Inc. All SPARC trademarks are used under license and  */ 
/* are trademarks or registered trademarks of SPARC International, Inc. in    */ 
/* the United States and other countries. Products bearing SPARC trademarks   */ 
/* are based upon an architecture developed by Sun Microsystems, Inc.         */ 
/*                                                                            */ 
/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)vcd_signals.v
***
****************************************************************************
****************************************************************************/

// This is a convenient place to put signals to be dumped in VCD (signalscan)
//     files.  This entire module is dumped.
//
// Note: this module is a temporary workaround for VCS's non-support
//       of $dumpvars(<net>) .
module vcd_signals ;

    wire [31:0] cycle_count = Mclocks.cycle_count ;

    // Transitions on this signal cause dcc samples to be taken
    reg samplesig ;
    initial begin
	samplesig = 0 ;
	forever @Mclocks.samplesig samplesig = ~samplesig ;
    end

`ifdef GATELEVEL
`else
    // For dcc_instr
    wire [7:0] instr_byte0 = Mdcc_bp.instr_byte0 ;
    wire [7:0] instr_byte1 = Mdcc_bp.instr_byte1 ;
    wire [7:0] instr_byte2 = Mdcc_bp.instr_byte2 ;
    wire [7:0] instr_byte3 = Mdcc_bp.instr_byte3 ;
    wire [7:0] instr_byte4 = Mdcc_bp.instr_byte4 ;
    wire [7:0] instr_byte5 = Mdcc_bp.instr_byte5 ;
    wire [7:0] instr_byte6 = Mdcc_bp.instr_byte6 ;
    wire [7:0] instr_byte7 = Mdcc_bp.instr_byte7 ;
    wire [7:0] instr_byte8 = Mdcc_bp.instr_byte8 ;
    wire [7:0] instr_byte9 = Mdcc_bp.instr_byte9 ;
    wire [7:0] instr_byte10 = Mdcc_bp.instr_byte10 ;
    wire [7:0] instr_byte11 = Mdcc_bp.instr_byte11 ;
    wire [7:0] instr_byte12 = Mdcc_bp.instr_byte12 ;
    wire [7:0] instr_byte13 = Mdcc_bp.instr_byte13 ;
    wire [7:0] instr_byte14 = Mdcc_bp.instr_byte14 ;
    wire [7:0] instr_byte15 = Mdcc_bp.instr_byte15 ;
    wire [7:0] instr_byte16 = Mdcc_bp.instr_byte16 ;
    wire [7:0] instr_byte17 = Mdcc_bp.instr_byte17 ;
    wire [7:0] instr_byte18 = Mdcc_bp.instr_byte18 ;
    wire [7:0] instr_byte19 = Mdcc_bp.instr_byte19 ;
    wire [7:0] instr_byte20 = Mdcc_bp.instr_byte20 ;
    wire [7:0] instr_byte21 = Mdcc_bp.instr_byte21 ;
    wire [7:0] instr_byte22 = Mdcc_bp.instr_byte22 ;
    wire [7:0] instr_byte23 = Mdcc_bp.instr_byte23 ;
    wire [7:0] instr_byte24 = Mdcc_bp.instr_byte24 ;
    wire [7:0] instr_byte25 = Mdcc_bp.instr_byte25 ;
    wire [7:0] instr_byte26 = Mdcc_bp.instr_byte26 ;
    wire [7:0] instr_byte27 = Mdcc_bp.instr_byte27 ;
    wire [7:0] instr_byte28 = Mdcc_bp.instr_byte28 ;
`endif

endmodule