--
--  File: C:\Fndtn\Active\projects\ACADEMY\stmach_v.vhd
-- created: 10/18/98 16:05:25
--  from: 'C:\Fndtn\Active\projects\ACADEMY\stmach_v.asf'
--  by fsm2hdl - version: 2.0.1.49
--
library IEEE;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library SYNOPSYS;
use SYNOPSYS.ATTRIBUTES.all;

entity stmach_v is 
  port (CLK: in STD_LOGIC;
        reset: in STD_LOGIC;
        strtstop: in STD_LOGIC;
        clkout: out STD_LOGIC;
        rst: out STD_LOGIC);
end;

architecture stmach_v_arch of stmach_v is


-- BINARY ENCODED state machine: stopwtch
type stopwtch_type is (CLEAR, counting, start, stop, stopped, zero);
attribute enum_encoding : string;
attribute enum_encoding of stopwtch_type: type is
	"000 " &		-- CLEAR
	"001 " &		-- counting
	"010 " &		-- start
	"011 " &		-- stop
	"100 " &		-- stopped
	"101";		-- zero

signal stopwtch: stopwtch_type;

begin
--concurrent signal assignments
--diagram ACTIONS;


stopwtch_machine: process (CLK, reset)

begin

if reset = '1' then
	stopwtch <= CLEAR;
elsif CLK'event and CLK = '1' then
	case stopwtch is
		when CLEAR =>
			stopwtch <= zero;
		when counting =>
			if strtstop = '0' then
				stopwtch <= counting;
			elsif strtstop ='1' then
				stopwtch <= stop;
			end if;
		when start =>
			if strtstop = '1' then
				stopwtch <= start;
			elsif strtstop = '0' then
				stopwtch <= counting;
			end if;
		when stop =>
			if strtstop = '1' then
				stopwtch <= stop;
			elsif strtstop = '0' then
				stopwtch <= stopped;
			end if;
		when stopped =>
			if strtstop = '0' then
				stopwtch <= stopped;
			elsif strtstop = '1' then
				stopwtch <= start;
			end if;
		when zero =>
			if strtstop = '0' then
				stopwtch <= zero;
			elsif strtstop = '1' then
				stopwtch <= start;
			end if;
		when others =>
			null;
	end case;
end if;
end process;

-- signal assignment statements for combinatorial outputs
clkout_assignment:
clkout <= '1' when (stopwtch = counting) else
          '1' when (stopwtch = start) else
          '0' when (stopwtch = stop) else
          '0' when (stopwtch = stopped) else
          '0' when (stopwtch = zero) else
          '0';

rst_assignment:
rst <= '0' when (stopwtch = counting) else
       '0' when (stopwtch = start) else
       '0' when (stopwtch = stop) else
       '0' when (stopwtch = stopped) else
       '0' when (stopwtch = zero) else
       '1';

end stmach_v_arch;