[Paths]
EXE=C:\fndtn\Active\exe
LIBDIR=C:\FNDTN\ACTIVE
LibID=C:\FNDTN\ACTIVE
SYSLIB=C:\FNDTN\ACTIVE\SYSLIB
PROJECTS=C:\FNDTN\ACTIVE\PROJECTS\
VHDLDat=C:\FNDTN\ACTIVE\VHDL
Editor=C:\fndtn\Active\exe\RBROWSER.EXE
[Net Attributes]
COLLAPSE=
KEEP=
NOREDUCE=
PERIOD=
PWR_MODE=
S=
TIG=
TNM=
TPSYNC=
TPTHRU=
COLLAPSE=
KEEP=
NOREDUCE=
PERIOD=
PWR_MODE=
S=
TIG=
TNM=
TPSYNC=
TPTHRU= 
[UserData]
User=Foundation Software Marketing
Company=Xilinx
[Schematic]
Raster On=ON
Add Libraries=OFF
Grid Color=8
Select Color=12
Select Wire Color=12
Pin Name Color=9
Pin Number Color=12
Symbol Name Color=2
Symbol Reference Color=2
Symbol Parameters Color=0
Symbol Technology Color=13
Symbol Color I=0
Symbol Color II=7
Symbol Color (empty)=4
Symbol Color (netlist)=5
Symbol Color (schematic)=1
Switch Symbol Color=12
Wire Color=9
Wire Edit Color=0
Junction Color=11
Xblox Pin Color=2
In Line Net Name Color=9
Net Name Color=2
PWR Color=0
Terminal Color=0
Terminal Name Color=2
Bus Color=4
Bus Name Color=2
Bus Tap Color=1
Default Graphics Color=0
Background Color=0
Pin Font=0
Pin Font Face=0
Symbol Name=1
Symbol Name Face=0
Symbol Reference=1
Symbol Reference Face=0
Symbol Parameters=1
Symbol Parameters Face=0
Net Name=0
Net Name Face=0
Terminal Name=0
Terminal Name Face=0
Bus Name=1
Bus Name Face=0
Graphics Font=0
Graphics Font Face=0
Small Font Height=20
Regular Font Height=35
Large Font Height=50
Visible Font Minimal Height=5
Wire Line Style=1
Wire Line Width=1
Junction Size=8
Junction Type=0
Xblox Wire Line Style=1
Xblox Wire Line Width=8
Xblox Junction Size=12
Xblox Junction Type=0
Autorouting time (sec/wire)=10
Wire Correction=ON
Check Pin Type=ON
Orthogonal Wires=ON
Autorouting=ON
Check Chip Crossing=ON
Bus Line Width=8
Bus Tap Type=3
Bus Left Range=7
Bus Right Range=0
Bus Corners=OFF
Symbol Line Style I=1
Symbol Line Style II=1
Graphics Line Style=1
Automatic Backup (min)=5
Symbol AutoBox Width=4
Allow symbol overlap=ON
Allow wires overlap=ON
Thick Line Width=7
Simulation step (ns)=0
Interactive mode=ON
Defer to audit file=OFF
Internal Warnings=OFF
Snap to Grid=ON
Create TEMP Symbols=ON
Delete Wires with Symbol=OFF
Status Line=ON
Command Line=ON
Coordinates=ON
Button Menu=ON
Button Horizontal=3
Ruler=OFF
Ruler Mark=2
Ruler Mark Width=1
Graphics=ON
Table=ON
Symbol Text=ON
Beep on Error=ON
Print frame=ON
Print 4 page tile=1
Printing margin=5
Print copies=1
Print whole project=1
Print All Black=ON
Sheet Format=18
Vertical Zones=8
Horizontal Zones=8
Grid Active=OFF
Grid Step=4
Grid Style=0
CrossHair Cursor=OFF
Maximized=OFF
Window=57, 50, 962, 711
Save on Exit=ON
hidden pins=OFF
[SC_ALV_options]
recursive=YES
ignore_builtin=NO
remove_busbox=YES
autopinname=YES
autopin=YES
xblox_bus=YES
invisible_refname=NO
ignore_internal_prop=YES
[Flow]
FSM_X6=On
[EXTENSIONS]
LastDirectory=C:\FNDTN\ACTIVE\PROJECTS
InitDialog=On
;XABELNETLIST=PLUSASM
;XABELNETLIST=PLUSASM
[Interactive]
Logfile=C:\FNDTN\ACTIVE\PROJECTS\ALDEC.LOG
Options=1, 1, 1, 1, 0, 0, 0, 2, 1, 1, 0, 0
Lines=200
Colors=16711935,255,16711680,0,0,0,0,0,
View=1,0
Console=0, 0, 0, 0, 0, 0, 0, , 0, 0
Errors=0, 0, 0, 0, 0, 0, 0, , 0, 0
Warnings=0, 0, 0, 0, 0, 0, 0, , 0, 0
Messages=0, 0, 0, 0, 0, 0, 0, , 0, 0
[Synthesis]
Exemplar=NO
Asyl=NO
internal_VHDL_check=NO
[Suspro]
Netkey=0
Active=16
Key=5
KeyEx=H9B1CABABABACEB9CABABABABABABABAHEBAB1HABABABABAWAKGL1M9R9M9T9L1BUBUBABABABABABA
[Pcm]
type=XILINX8
[ABEL]
ViewFiles=On
[LogiBLOX]
show_pinbus_names=YES
[Library_List]
151=C:\FNDTN\ACTIVE\SYSLIB\XC3000
153=C:\FNDTN\ACTIVE\SYSLIB\XC4000E
157=C:\FNDTN\ACTIVE\SYSLIB\XC5200
167=C:\FNDTN\ACTIVE\SYSLIB\Spartan
169=C:\FNDTN\ACTIVE\SYSLIB\SpartanX
171=C:\FNDTN\ACTIVE\SYSLIB\Virtex
161=C:\FNDTN\ACTIVE\SYSLIB\XC9500
1001=C:\FNDTN\ACTIVE\PROJECTS\WATCHVER\LIB\WATCHVER
1002=C:\FNDTN\ACTIVE\PROJECTS\WATCH_SC\LIB\WATCH_SC
1003=C:\FNDTN\ACTIVE\PROJECTS\TEST\LIB\TEST
1004=C:\FNDTN\ACTIVE\PROJECTS\TEST2\LIB\TEST2
1005=C:\FNDTN\ACTIVE\PROJECTS\X_WATVER\LIB\X_WATVER
1006=C:\FNDTN\ACTIVE\PROJECTS\DATATAPE\LIB\DATATAPE
1007=C:\FNDTN\ACTIVE\PROJECTS\HARDY\LIB\HARDY
1008=C:\FNDTN\ACTIVE\PROJECTS\IH009\LIB\IH009
1009=C:\FNDTN\ACTIVE\PROJECTS\SORT12\LIB\SORT12
1011=C:\FNDTN\ACTIVE\PROJECTS\TEST1\LIB\TEST1
155=C:\FNDTN\ACTIVE\SYSLIB\XC4000X
133=C:\FNDTN\ACTIVE\SYSLIB\SIMPRIMS
149=C:\FNDTN\ACTIVE\SYSLIB\XABELSIM
1010=C:\FNDTN\ACTIVE\PROJECTS\IV014\LIB\IV014
1012=C:\FNDTN\ACTIVE\PROJECTS\X_WATCH\LIB\X_WATCH
1013=C:\FNDTN\ACTIVE\PROJECTS\ACADEMY\LIB\ACADEMY
[HDESettings]
Tabulation=8
Highlighting=1
LineNumbers=1
Margin=1
AutoIndent=1
AutoScanning=1
ErrorsDesciption=0
Language=VHDL
Compiler=METAMOR
Font=0,0,0,0,0,0,0,0,0,0,0,0,0,Fixedsys
ShowPropFonts=1
WorkingDir=C:\Fndtn\Active\projects\watch_sc\
[HDEColors]
NormalCol=0
CommentCol=6
KeywordCol=4
ConstantCol=8
DirectivesCol=2
MetaSymbolCol=0
[HDELA2]
State=0
Mode=1
WT=64
WB=330
WR=459
WL=26
TT=2
TB=211
TR=212
TL=2
PT=2
PB=211
PR=425
PL=215
[HDE Recent File List]
File1=C:\FNDTN\ACTIVE\PROJECTS\ACADEMY\HEX2LED.vhd
File2=c:\fndtn\active\projects\x_watver\smallcntr.v
File3=c:\fndtn\active\projects\watchver\hex2led.v
File4=d:\jkl\max9_b~1\hardy\test3\zerocnt8.vhd
[PCM_Window]
Left=46
Top=4
Width=886
Height=736
Maximized=Off
LeftWidth=209
UpHeight=383
Settings=On
[xilinx]
family=2
xfam=XC4000XL
libraries=unified
[device]
part=4013XLBG256-08
xilinx=4013XLBG256-08
[Netlist]
ExpFormat=Edif 200
[dpm32]
[Symbol Editor]
Maximized=NO
Left=0
Right=768
Top=0
Bottom=537
grid=off
disp_pwr=off
disp_pin_name=on
disp_pin_number=on
toolbar=on
statusbar=on
invisible_pins=on
[TOOLBOXES]
CHANGES=HIDE 924 50 50 132
SYMBOLS=HIDE 512 215 130 390
WIRES=HIDE 924 50 50 132
GRAPHICS=HIDE 852 50 122 60
PROBES=HIDE 193 343 98 60
QUERY=HIDE 749 10 225 271
VHE=HIDE 924 50 50 108
[FSM ToolBars-Summary]
Bars=6
[FSM Recent File List]
File1=C:\FNDTN\ACTIVE\PROJECTS\X_WATCH\STMACH_V.asf
File2=C:\FNDTN\ACTIVE\PROJECTS\WATCH_SC\STMACH_V.asf
File3=C:\FNDTN\ACTIVE\PROJECTS\WATCH_SC\STMACH_V.asf
[FSM Settings]
TextScaling=NO
StateCodes=YES
Language=VHDL
LoadOnActivate=YES
[Pin Parameters]
PINTYPE=
PORT_ID=
[LM]
bDelLib=YES
bDetLib=YES
bDelObj=YES
bLibSrc=YES
bObjSrc=YES
[Symbol Parameters]
$FILE=
$DEF=
$BUSDELIMITER=
EXT=
LEVEL=
LIBVER=
DEF=
LOC=
DEVICE=
BUS_WIDTH=
STYLE=
OPTYPE=
ENCODING=
ASYNC_VAL=
MODTYPE=
BLKNM=
DIVIDE1_BY=
DIVIDE2_BY=
FAST=
INIT=
NODELAY=
PWR_MODE=
RLOC=
SLOW=
TNM=
[FSM ToolBars-Bar0]
BarID=59393
[FSM ToolBars-Bar1]
BarID=59419
Bars=3
Bar#0=0
Bar#1=59392
Bar#2=0
[FSM ToolBars-Bar2]
BarID=59420
Bars=4
Bar#0=0
Bar#1=59424
Bar#2=0
Bar#3=59425
[FSM ToolBars-Bar3]
BarID=59392
XPos=-2
YPos=-2
[FSM ToolBars-Bar4]
BarID=59425
XPos=-2
YPos=-2
[FSM ToolBars-Bar5]
BarID=59424
Visible=0
XPos=-8
YPos=-117
[Simulator]
External Editor=C:\fndtn\Active\exe\MACROED.EXE
Extended Options=Off
main=CONF_NORMAL, 35, 91, 961, 635
toolbox=CONF_POSITION, 91, 0, 0, 0
showhier=CONF_HIDE, 0, 0, 0, 0
tv0=CONF_NORMAL, 0, 0, 760, 420, 5, 56
Step=1000
Binary Counter=Off
Status Bar=On
Ruler=On
End of Step Estimation=On
Breakpoints Enabled=Off
Prompt for Browsing Netlist Log=On
Prompt for Loading Last Session=On
Display Hidden Nets=Off
Backup Frequency=300
Backup=On
Netlist Log Messages=All
Error Reporting Options=9CE7
[Projects List]
c:\fndtn\active\projects\academy=academy
c:\fndtn\active\projects\watchver=watchver
c:\fndtn\active\projects\watch_sc=watch_sc
c:\fndtn\active\projects\x_watver=x_watver
c:\fndtn\active\projects\x_watch=x_watch
c:\fndtn\active\projects\iv014=iv014
c:\fndtn\active\projects\datatape=datatape
c:\fndtn\active\projects\sort12=sort12
c:\fndtn\active\projects\hardy=hardy
c:\fndtn\active\projects\ih009=ih009
c:\fndtn\active\projects\test1=test1
c:\fndtn\active\projects\test2=test2
c:\fndtn\active\projects\test=test
[Recent Projects]
c:\fndtn\active\projects\academy.pdf= 
c:\fndtn\active\projects\watchver.pdf= 
c:\fndtn\active\projects\watch_sc.pdf= 
c:\fndtn\active\projects\x_watver.pdf=