[Paths]
EXE=C:\Xilinx\Active\exe
LIBDIR=C:\XILINX\ACTIVE
LibID=C:\XILINX\ACTIVE
SYSLIB=C:\XILINX\ACTIVE\SYSLIB
PROJECTS=C:\XILINX\ACTIVE\PROJECTS\
VHDLDat=C:\XILINX\ACTIVE\VHDL
Editor=C:\Xilinx\Active\exe\RBROWSER.EXE
[Net Attributes]
COLLAPSE=
KEEP=
NOREDUCE=
PERIOD=
PWR_MODE=
S=
TIG=
TNM=
TPSYNC=
TPTHRU=
COLLAPSE=
KEEP=
NOREDUCE=
PERIOD=
PWR_MODE=
S=
TIG=
TNM=
TPSYNC=
TPTHRU= 
[UserData]
User=frank nelson
Company=xilinx
[Schematic]
Grid Color=8
Select Color=12
Select Wire Color=12
Pin Name Color=9
Pin Number Color=12
Symbol Name Color=2
Symbol Reference Color=2
Symbol Parameters Color=0
Symbol Technology Color=13
Symbol Color I=0
Symbol Color II=7
Symbol Color (empty)=4
Symbol Color (netlist)=5
Symbol Color (schematic)=1
Switch Symbol Color=12
Wire Color=9
Wire Edit Color=0
Junction Color=11
Xblox Pin Color=2
In Line Net Name Color=9
Net Name Color=2
PWR Color=0
Terminal Color=0
Terminal Name Color=2
Bus Color=4
Bus Name Color=2
Bus Tap Color=1
Default Graphics Color=0
Background Color=0
Pin Font=0
Pin Font Face=0
Symbol Name=1
Symbol Name Face=0
Symbol Reference=1
Symbol Reference Face=0
Symbol Parameters=1
Symbol Parameters Face=0
Net Name=0
Net Name Face=0
Terminal Name=0
Terminal Name Face=0
Bus Name=1
Bus Name Face=0
Graphics Font=0
Graphics Font Face=0
Small Font Height=20
Regular Font Height=35
Large Font Height=50
Visible Font Minimal Height=5
Wire Line Style=1
Wire Line Width=1
Junction Size=8
Junction Type=0
Xblox Wire Line Style=1
Xblox Wire Line Width=8
Xblox Junction Size=12
Xblox Junction Type=0
Autorouting time (sec/wire)=10
Wire Correction=ON
Check Pin Type=ON
Orthogonal Wires=ON
Autorouting=ON
Check Chip Crossing=ON
Bus Line Width=8
Bus Tap Type=3
Bus Left Range=7
Bus Right Range=0
Bus Corners=OFF
Symbol Line Style I=1
Symbol Line Style II=1
Graphics Line Style=1
Automatic Backup (min)=5
Symbol AutoBox Width=4
Allow symbol overlap=ON
Allow wires overlap=ON
Thick Line Width=7
Simulation step (ns)=0
Interactive mode=ON
Defer to audit file=OFF
Internal Warnings=OFF
Snap to Grid=ON
Create TEMP Symbols=ON
Delete Wires with Symbol=OFF
Status Line=ON
Command Line=ON
Coordinates=ON
Button Menu=ON
Button Horizontal=3
Ruler=OFF
Ruler Mark=2
Ruler Mark Width=1
Graphics=ON
Table=ON
Symbol Text=ON
Beep on Error=ON
Print frame=OFF
Print 4 page tile=1
Printing margin=5
Print copies=1
Print whole project=1
Print All Black=ON
Sheet Format=15
Vertical Zones=8
Horizontal Zones=8
Grid Active=OFF
Grid Step=4
Grid Style=0
CrossHair Cursor=OFF
Maximized=ON
Window=96, 96, 696, 504
Save on Exit=ON
hidden pins=OFF
Raster On=ON
Add Libraries=OFF
Table01=Project
Table02=Macro
Table03=Date
[SC_ALV_options]
recursive=YES
ignore_builtin=NO
remove_busbox=YES
autopinname=YES
autopin=YES
xblox_bus=YES
invisible_refname=NO
ignore_internal_prop=YES
[Flow]
FSM_X6=On
[EXTENSIONS]
LastDirectory=C:\NM1LABS\BTC
InitDialog=Off
;XABELNETLIST=PLUSASM
;XABELNETLIST=PLUSASM
[Interactive]
Logfile=C:\XILINX\ACTIVE\PROJECTS\ALDEC.LOG
Options=1, 1, 1, 1, 0, 0, 0, 2, 1, 1, 0, 0
Lines=200
Colors=16711935,255,16711680,0,0,0,0,0,
View=1,0
Console=0, 0, 0, 0, 0, 0, 0, , 0, 0
Errors=0, 0, 0, 0, 0, 0, 0, , 0, 0
Warnings=0, 0, 0, 0, 0, 0, 0, , 0, 0
Messages=0, 0, 0, 0, 0, 0, 0, , 0, 0
[Synthesis]
Exemplar=NO
Asyl=NO
internal_VHDL_check=NO
[Suspro]
Netkey=0
Active=16
Key=5
KeyEx=H9B1CABABABACEB9CABABABABABABABAHEBAB1HABABABABAWAKGL1M9R9M9T9L1BUBUBABABABABABA
[Pcm]
type=XILINX8
[ABEL]
ViewFiles=On
[LogiBLOX]
show_pinbus_names=YES
[Library_List]
169=C:\XILINX\ACTIVE\SYSLIB\SpartanX
1001=C:\XILINX\ACTIVE\PROJECTS\WATCH_SC\LIB\WATCH_SC
1002=C:\XILINX\ACTIVE\PROJECTS\WTUT_SC\LIB\WTUT_SC
1003=C:\FNDLAB~2\UNTITLED\LIB\UNTITLED
1004=C:\XILINX\ACTIVE\PROJECTS\WATCHVHD\LIB\WATCHVHD
153=C:\XILINX\ACTIVE\SYSLIB\XC4000E
155=C:\XILINX\ACTIVE\SYSLIB\XC4000X
157=C:\XILINX\ACTIVE\SYSLIB\XC5200
167=C:\XILINX\ACTIVE\SYSLIB\Spartan
171=C:\XILINX\ACTIVE\SYSLIB\Virtex
161=C:\XILINX\ACTIVE\SYSLIB\XC9500
133=C:\XILINX\ACTIVE\SYSLIB\SIMPRIMS
149=C:\XILINX\ACTIVE\SYSLIB\XABELSIM
1005=C:\EXTRA\WTUT_SC\LIB\WTUT_SC
1006=C:\NM1LABS\LGBLOX\WATCH\LIB\WATCH
1007=C:\XILINX\ACTIVE\PROJECTS\WATCH\LIB\WATCH
1008=C:\TEST\WATCH\LIB\WATCH
1009=C:\NM1LABS\BTC\WATCH\LIB\WATCH
[PCM_Window]
Left=111
Top=38
Width=612
Height=489
Maximized=Off
LeftWidth=178
UpHeight=330
Settings=On
[LM]
bDelLib=YES
bDetLib=YES
bDelObj=YES
bLibSrc=YES
bObjSrc=YES
[xilinx]
family=2
xfam=XC4000E
libraries=unified
[HDESettings]
Tabulation=8
Highlighting=1
LineNumbers=1
Margin=1
AutoIndent=1
AutoScanning=1
ErrorsDesciption=0
Language=VHDL
Compiler=METAMOR
Font=0,0,0,0,0,0,0,0,0,0,0,0,0,Fixedsys
ShowPropFonts=1
WorkingDir=
[HDEColors]
NormalCol=0
CommentCol=6
KeywordCol=4
ConstantCol=8
DirectivesCol=2
MetaSymbolCol=0
[HDELA2]
State=0
Mode=1
WT=164
WB=432
WR=557
WL=124
TT=2
TB=211
TR=212
TL=2
PT=2
PB=211
PR=425
PL=215
[HDE Recent File List]
File1=C:\EXTRA\WTUT_SC\STMACH_V.VHD
File2=C:\XILINX\ACTIVE\PROJECTS\WATCH_SC\STMACH_V.VHD
File3=C:\EXTRA\WTUT_SC\HEX2LED.vhd
File4=C:\XILINX\ACTIVE\PROJECTS\WATCH_SC\HEX2LED.vhd
[TOOLBOXES]
CHANGES=HIDE 700 50 50 133
SYMBOLS=HIDE 140 113 152 302
WIRES=HIDE 700 50 50 133
GRAPHICS=HIDE 628 50 122 61
PROBES=HIDE 652 50 98 61
QUERY=HIDE 60 249 243 271
VHE=HIDE 700 50 50 109
[Symbol Editor]
Maximized=NO
Left=6
Right=648
Top=28
Bottom=456
grid=off
disp_pwr=off
disp_pin_name=on
disp_pin_number=on
toolbar=on
statusbar=on
invisible_pins=on
[FSM ToolBars-Summary]
Bars=6
[FSM Recent File List]
File1=C:\EXTRA\WTUT_SC\STMACH_V.asf
File2=C:\XILINX\ACTIVE\PROJECTS\WATCH_SC\STMACH_V.asf
[FSM Settings]
TextScaling=NO
StateCodes=YES
Language=VHDL
LoadOnActivate=YES
[device]
part=4003EPC84-3
xilinx=4003EPC84-3
[PCM_FONT]
lfHeight=-15
lfWidth=0
lfWeight=400
lfItalic=0
lfCharSet=0
lfPitchAndFamily=34
lfFaceName=Arial
[Netlist]
ExpFormat=Edif 200
[Pin Parameters]
PINTYPE=
PORT_ID=
PARAM=
[Simulator]
External Editor=C:\Xilinx\Active\exe\MACROED.EXE
Extended Options=Off
main=CONF_NORMAL, 79, 69, 604, 447
toolbox=CONF_POSITION, 69, 0, 0, 0
showhier=CONF_HIDE, 0, 0, 0, 0
tv0=CONF_MAXMIZE, 0, 0, 534, 201, 20, 56
Step=500
Binary Counter=Off
Status Bar=On
Ruler=On
End of Step Estimation=On
Breakpoints Enabled=Off
Prompt for Browsing Netlist Log=On
Prompt for Loading Last Session=On
Display Hidden Nets=Off
Backup Frequency=300
Backup=On
Netlist Log Messages=All
Error Reporting Options=9CE7
[FSM ToolBars-Bar0]
BarID=59393
[FSM ToolBars-Bar1]
BarID=59419
Bars=3
Bar#0=0
Bar#1=59392
Bar#2=0
[FSM ToolBars-Bar2]
BarID=59420
Bars=4
Bar#0=0
Bar#1=59424
Bar#2=0
Bar#3=59425
[FSM ToolBars-Bar3]
BarID=59392
XPos=-2
YPos=-2
[FSM ToolBars-Bar4]
BarID=59425
XPos=-2
YPos=-2
[FSM ToolBars-Bar5]
BarID=59424
Visible=0
XPos=-8
YPos=-121
[Projects List]
c:\nm1labs\btc\watch=watch
c:\test\watch=watch
c:\nm1labs\lgblox\watch=watch
c:\xilinx\active\projects\watch=watch
c:\extra\wtut_sc=wtut_sc
c:\xilinx\active\projects\watch_sc=watch_sc
c:\xilinx\active\projects\wtut_sc=wtut_sc
c:\xilinx\active\projects\watchvhd=watchvhd
c:\fndlab~2\untitled=untitled
[Recent Projects]
c:\nm1labs\btc\watch.pdf= 
c:\test\watch.pdf= 
c:\nm1labs\lgblox\watch.pdf= 
c:\xilinx\active\projects\watch.pdf= 
[Symbol Parameters]
$FILE=
$DEF=
$BUSDELIMITER=
EXT=
LEVEL=
LIBVER=
LOC=
DEVICE=
PINORDER=
SIMMODEL=
VHDL=
BUS_WIDTH=
STYLE=
OPTYPE=
ENCODING=
ASYNC_VAL=
MODTYPE=
DEF=
BLKNM=
DIVIDE1_BY=
DIVIDE2_BY=
FAST=
INIT=
NODELAY=
PWR_MODE=
RLOC=