METAMOR VHDL Logic Compiler 3.0.5 (11/28/97)
Copyright (c) 1992-97 Metamor, Inc. All Rights Reserved
Compiling for: Xilinx EDIF , Macrocell inference
analyze....                           1 sec
elaborate design "hex2led"
   assign  :                          0 sec
elaborate "hex2led"                   0 sec
optimize "hex2led"....                3 sec
   combinational logic area estimate = 19 LUTs
format....                            0 sec
no errors.
compile time = 4 sec
peak dynamic memory allocation = 1.160 Mbyte.