METAMOR VHDL Logic Compiler 3.0.5 (11/28/97)
Copyright (c) 1992-97 Metamor, Inc. All Rights Reserved
Compiling for: Xilinx EDIF 
analyze....                           4 sec
elaborate design "stopwtch"
   process :                          1 sec
     Inferred structure :
       flip flop: ar       stopwtch 2        stopwtch.VHD line 52
       flip flop: ar       stopwtch 1        stopwtch.VHD line 52
       flip flop: ar       stopwtch 0        stopwtch.VHD line 52
   assign  :                          0 sec
   assign  :                          0 sec
elaborate "stopwtch"                  1 sec
optimize "stopwtch"....               2 sec
   flip flops with asynchronous reset = 3
   combinational logic area estimate = 9 LUTs
format....                            0 sec
no errors.
compile time = 7 sec
peak dynamic memory allocation = 2.501 Mbyte.