Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 16 secs Finished initial Placement phase. REAL time: 16 secs Starting Constructive Placer. REAL time: 17 secs Placer score = 758271 Placer score = 507499 Placer score = 493131 Placer score = 454077 Placer score = 415638 Placer score = 396262 Placer score = 372115 Placer score = 362926 Placer score = 334704 Placer score = 316531 Placer score = 307361 Placer score = 280109 Placer score = 275877 Placer score = 265451 Placer score = 250857 Placer score = 246086 Placer score = 239061 Placer score = 226869 Placer score = 219616 Placer score = 217053 Placer score = 203485 Placer score = 202950 Placer score = 196730 Placer score = 192764 Placer score = 188208 Placer score = 186474 Placer score = 183824 Placer score = 183676 Placer score = 182691 Placer score = 179720 Placer score = 179534 Placer score = 177388 Placer score = 176776 Placer score = 176546 Placer score = 175519 Placer score = 175039 Placer score = 175009 Finished Constructive Placer. REAL time: 8 mins 31 secs Writing design to file "../p1.dir/4_4_1.ncd". Starting Optimizing Placer. REAL time: 8 mins 31 secs Optimizing .. Swapped 22 comps. Xilinx Placer [1] 174708 REAL time: 9 mins 1 secs Optimizing .. Swapped 2 comps. Xilinx Placer [2] 174708 REAL time: 9 mins 31 secs Finished Optimizing Placer. REAL time: 9 mins 31 secs Writing design to file "../p1.dir/4_4_1.ncd". Total REAL time to Placer completion: 9 mins 32 secs Total CPU time to Placer completion: 9 mins 30 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 48 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1772124) REAL time: 10 mins 20 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (14190) REAL time: 11 mins 15 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (12474) REAL time: 13 mins 1 secs End of iteration 4 3402 successful; 0 unrouted; (11354) REAL time: 14 mins 33 secs Writing design to file "../p1.dir/4_4_1.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (11381) REAL time: 16 mins 2 secs Writing design to file "../p1.dir/4_4_1.ncd". Total REAL time: 16 mins 2 secs Total CPU time: 15 mins 58 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 16 mins 5 secs Total CPU time to Router completion: 16 mins 1 secs Generating PAR statistics. Timing Score: 11381 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 23.011ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p1.dir/4_4_1.ncd". All signals are completely routed. Total REAL time to PAR completion: 16 mins 14 secs Total CPU time to PAR completion: 16 mins 9 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 2 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 799264 Placer score = 551354 Placer score = 501945 Placer score = 477070 Placer score = 447908 Placer score = 423692 Placer score = 406403 Placer score = 387652 Placer score = 378227 Placer score = 339933 Placer score = 337815 Placer score = 319122 Placer score = 301077 Placer score = 292643 Placer score = 277346 Placer score = 274217 Placer score = 267683 Placer score = 251952 Placer score = 243440 Placer score = 237113 Placer score = 222175 Placer score = 220047 Placer score = 216361 Placer score = 210983 Placer score = 203610 Placer score = 199697 Placer score = 198430 Placer score = 195142 Placer score = 194079 Placer score = 193158 Placer score = 191773 Placer score = 190290 Placer score = 188908 Placer score = 187329 Placer score = 187113 Placer score = 186664 Placer score = 185405 Placer score = 184825 Placer score = 184445 Placer score = 184265 Placer score = 184145 Finished Constructive Placer. REAL time: 8 mins 39 secs Writing design to file "../p1.dir/4_4_2.ncd". Starting Optimizing Placer. REAL time: 8 mins 39 secs Optimizing .. Swapped 10 comps. Xilinx Placer [3] 184015 REAL time: 9 mins 9 secs Finished Optimizing Placer. REAL time: 9 mins 9 secs Writing design to file "../p1.dir/4_4_2.ncd". Total REAL time to Placer completion: 9 mins 10 secs Total CPU time to Placer completion: 9 mins 9 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 25 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (2352161) REAL time: 9 mins 56 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (31996) REAL time: 11 mins 15 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (19871) REAL time: 13 mins 41 secs End of iteration 4 3402 successful; 0 unrouted; (17961) REAL time: 15 mins 38 secs Writing design to file "../p1.dir/4_4_2.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (17961) REAL time: 17 mins 28 secs Writing design to file "../p1.dir/4_4_2.ncd". Total REAL time: 17 mins 29 secs Total CPU time: 17 mins 26 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 32 secs Total CPU time to Router completion: 17 mins 29 secs Generating PAR statistics. Timing Score: 17961 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 24.087ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p1.dir/4_4_2.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 41 secs Total CPU time to PAR completion: 17 mins 37 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 3 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 10 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 11 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 723904 Placer score = 555097 Placer score = 523185 Placer score = 465056 Placer score = 427497 Placer score = 419905 Placer score = 386022 Placer score = 380636 Placer score = 353781 Placer score = 336468 Placer score = 323988 Placer score = 320548 Placer score = 290101 Placer score = 277004 Placer score = 270617 Placer score = 257415 Placer score = 242744 Placer score = 238265 Placer score = 228186 Placer score = 218591 Placer score = 211730 Placer score = 203765 Placer score = 200325 Placer score = 195491 Placer score = 192056 Placer score = 190946 Placer score = 190863 Placer score = 186355 Placer score = 185172 Placer score = 184627 Placer score = 184322 Placer score = 183566 Placer score = 183056 Placer score = 180347 Placer score = 179193 Placer score = 178123 Placer score = 177107 Placer score = 176595 Placer score = 176447 Placer score = 176146 Placer score = 176096 Placer score = 176057 Placer score = 175816 Placer score = 175606 Placer score = 174958 Placer score = 174617 Placer score = 174446 Placer score = 174386 Finished Constructive Placer. REAL time: 8 mins 59 secs Writing design to file "../p1.dir/4_4_3.ncd". Starting Optimizing Placer. REAL time: 9 mins Optimizing .. Swapped 16 comps. Xilinx Placer [4] 174127 REAL time: 9 mins 30 secs Finished Optimizing Placer. REAL time: 9 mins 30 secs Writing design to file "../p1.dir/4_4_3.ncd". Total REAL time to Placer completion: 9 mins 32 secs Total CPU time to Placer completion: 9 mins 27 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 50 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (2167322) REAL time: 10 mins 24 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (30629) REAL time: 11 mins 49 secs Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (13642) REAL time: 14 mins 13 secs End of iteration 4 3402 successful; 0 unrouted; (9196) REAL time: 16 mins 17 secs Writing design to file "../p1.dir/4_4_3.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (9196) REAL time: 17 mins 49 secs Writing design to file "../p1.dir/4_4_3.ncd". Total REAL time: 17 mins 50 secs Total CPU time: 17 mins 35 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 54 secs Total CPU time to Router completion: 17 mins 38 secs Generating PAR statistics. Timing Score: 9196 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 23.474ns | 7 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p1.dir/4_4_3.ncd". All signals are completely routed. Total REAL time to PAR completion: 18 mins 3 secs Total CPU time to PAR completion: 17 mins 46 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 4 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 795088 Placer score = 535835 Placer score = 492670 Placer score = 445449 Placer score = 423620 Placer score = 391839 Placer score = 377774 Placer score = 357894 Placer score = 340879 Placer score = 335132 Placer score = 312988 Placer score = 288955 Placer score = 272358 Placer score = 264484 Placer score = 257333 Placer score = 244572 Placer score = 231133 Placer score = 218635 Placer score = 210559 Placer score = 209152 Placer score = 200582 Placer score = 198907 Placer score = 198685 Placer score = 193523 Placer score = 192279 Placer score = 189391 Placer score = 189100 Placer score = 186996 Placer score = 186489 Placer score = 185047 Placer score = 182715 Placer score = 181109 Placer score = 180703 Placer score = 180223 Placer score = 179962 Placer score = 179722 Placer score = 179586 Placer score = 179288 Placer score = 178850 Placer score = 178340 Placer score = 178100 Placer score = 178054 Finished Constructive Placer. REAL time: 9 mins 39 secs Writing design to file "../p1.dir/4_4_4.ncd". Starting Optimizing Placer. REAL time: 9 mins 40 secs Optimizing .. Swapped 13 comps. Xilinx Placer [5] 177874 REAL time: 10 mins 11 secs Finished Optimizing Placer. REAL time: 10 mins 11 secs Writing design to file "../p1.dir/4_4_4.ncd". Total REAL time to Placer completion: 10 mins 12 secs Total CPU time to Placer completion: 10 mins 8 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 10 mins 28 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1846206) REAL time: 11 mins Improving timing. End of iteration 2 3402 successful; 0 unrouted; (35680) REAL time: 12 mins 6 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (15853) REAL time: 14 mins 4 secs End of iteration 4 3402 successful; 0 unrouted; (12894) REAL time: 15 mins 40 secs Writing design to file "../p1.dir/4_4_4.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (10164) REAL time: 17 mins 5 secs Writing design to file "../p1.dir/4_4_4.ncd". Total REAL time: 17 mins 6 secs Total CPU time: 17 mins 1 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 9 secs Total CPU time to Router completion: 17 mins 4 secs Generating PAR statistics. Timing Score: 10164 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 21.799ns | 7 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p1.dir/4_4_4.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 19 secs Total CPU time to PAR completion: 17 mins 13 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 4 (set by user) Placer effort level (-pl): 4 (default) Placer cost table entry (-t): 5 Router effort level (-rl): 4 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 754183 Placer score = 551797 Placer score = 505818 Placer score = 457539 Placer score = 432095 Placer score = 422974 Placer score = 392624 Placer score = 379694 Placer score = 344762 Placer score = 342905 Placer score = 331893 Placer score = 306433 Placer score = 288335 Placer score = 270203 Placer score = 266338 Placer score = 253241 Placer score = 240842 Placer score = 221689 Placer score = 210158 Placer score = 206671 Placer score = 204537 Placer score = 198047 Placer score = 195552 Placer score = 194146 Placer score = 189196 Placer score = 188735 Placer score = 187637 Placer score = 187078 Placer score = 186158 Placer score = 186130 Placer score = 184374 Placer score = 182191 Placer score = 182065 Placer score = 180618 Placer score = 180037 Placer score = 179709 Placer score = 179293 Placer score = 178577 Placer score = 177901 Placer score = 177691 Placer score = 177481 Placer score = 177361 Finished Constructive Placer. REAL time: 9 mins 18 secs Writing design to file "../p1.dir/4_4_5.ncd". Starting Optimizing Placer. REAL time: 9 mins 18 secs Optimizing .. Swapped 14 comps. Xilinx Placer [6] 177121 REAL time: 9 mins 50 secs Optimizing .. Swapped 2 comps. Xilinx Placer [7] 177121 REAL time: 10 mins 21 secs Finished Optimizing Placer. REAL time: 10 mins 21 secs Writing design to file "../p1.dir/4_4_5.ncd". Total REAL time to Placer completion: 10 mins 22 secs Total CPU time to Placer completion: 10 mins 21 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 10 mins 40 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (2063264) REAL time: 11 mins 13 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (30306) REAL time: 12 mins 23 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 2 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (23625) REAL time: 14 mins 35 secs End of iteration 4 3402 successful; 0 unrouted; (25166) REAL time: 16 mins 23 secs Writing design to file "../p1.dir/4_4_5.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 3 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (24448) REAL time: 17 mins 56 secs Writing design to file "../p1.dir/4_4_5.ncd". Total REAL time: 17 mins 57 secs Total CPU time: 17 mins 56 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 18 mins Total CPU time to Router completion: 17 mins 59 secs Generating PAR statistics. Timing Score: 24448 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 23.622ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p1.dir/4_4_5.ncd". All signals are completely routed. Total REAL time to PAR completion: 18 mins 8 secs Total CPU time to PAR completion: 18 mins 6 secs PAR done.