350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 12 secs Finished initial Timing Analysis. REAL time: 17 secs Starting initial Placement phase. REAL time: 20 secs Finished initial Placement phase. REAL time: 20 secs Starting Constructive Placer. REAL time: 21 secs Placer score = 723279 Placer score = 524443 Placer score = 515621 Placer score = 467690 Placer score = 437559 Placer score = 437453 Placer score = 372789 Placer score = 355043 Placer score = 327830 Placer score = 306427 Placer score = 286812 Placer score = 285849 Placer score = 275532 Placer score = 261236 Placer score = 249751 Placer score = 239389 Placer score = 233994 Placer score = 225277 Placer score = 210526 Placer score = 206055 Placer score = 203210 Placer score = 198838 Placer score = 194964 Placer score = 190534 Placer score = 189515 Placer score = 186214 Placer score = 185107 Placer score = 184396 Placer score = 183446 Placer score = 181267 Placer score = 180873 Placer score = 176849 Placer score = 176788 Placer score = 175588 Placer score = 175018 Placer score = 174778 Placer score = 174598 Placer score = 174478 Finished Constructive Placer. REAL time: 10 mins Writing design to file "../p2.dir/3_3_1.ncd". Starting Optimizing Placer. REAL time: 10 mins Optimizing ... Swapped 28 comps. Xilinx Placer [1] 174058 REAL time: 10 mins 35 secs Optimizing ... Swapped 2 comps. Xilinx Placer [2] 174058 REAL time: 11 mins 9 secs Finished Optimizing Placer. REAL time: 11 mins 9 secs Writing design to file "../p2.dir/3_3_1.ncd". Total REAL time to Placer completion: 11 mins 10 secs Total CPU time to Placer completion: 11 mins 2 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 11 mins 28 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (2042350) REAL time: 12 mins 11 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (37663) REAL time: 13 mins 38 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (9981) REAL time: 15 mins 58 secs End of iteration 4 3402 successful; 0 unrouted; (9444) REAL time: 17 mins 35 secs Writing design to file "../p2.dir/3_3_1.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (9444) REAL time: 19 mins 16 secs Writing design to file "../p2.dir/3_3_1.ncd". Total REAL time: 19 mins 17 secs Total CPU time: 19 mins 7 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 19 mins 20 secs Total CPU time to Router completion: 19 mins 10 secs Generating PAR statistics. Timing Score: 9444 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 22.287ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_1.ncd". All signals are completely routed. Total REAL time to PAR completion: 19 mins 29 secs Total CPU time to PAR completion: 19 mins 19 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 2 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 785224 Placer score = 556279 Placer score = 548839 Placer score = 515641 Placer score = 455235 Placer score = 419573 Placer score = 394606 Placer score = 363926 Placer score = 330773 Placer score = 308476 Placer score = 288297 Placer score = 274068 Placer score = 266858 Placer score = 256095 Placer score = 245217 Placer score = 242668 Placer score = 232350 Placer score = 221529 Placer score = 219013 Placer score = 215839 Placer score = 209691 Placer score = 206894 Placer score = 206345 Placer score = 200805 Placer score = 200354 Placer score = 197967 Placer score = 195965 Placer score = 194355 Placer score = 192886 Placer score = 191419 Placer score = 189475 Placer score = 186941 Placer score = 186751 Placer score = 186345 Placer score = 185575 Placer score = 184643 Placer score = 184142 Placer score = 183962 Placer score = 183782 Placer score = 183482 Finished Constructive Placer. REAL time: 8 mins 26 secs Writing design to file "../p2.dir/3_3_2.ncd". Starting Optimizing Placer. REAL time: 8 mins 26 secs Optimizing .. Swapped 22 comps. Xilinx Placer [3] 183122 REAL time: 8 mins 57 secs Optimizing .. Swapped 8 comps. Xilinx Placer [4] 182942 REAL time: 9 mins 27 secs Finished Optimizing Placer. REAL time: 9 mins 27 secs Writing design to file "../p2.dir/3_3_2.ncd". Total REAL time to Placer completion: 9 mins 28 secs Total CPU time to Placer completion: 9 mins 26 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 45 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1949164) REAL time: 10 mins 19 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (26964) REAL time: 11 mins 35 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 4 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (13319) REAL time: 13 mins 48 secs End of iteration 4 3402 successful; 0 unrouted; (12998) REAL time: 15 mins 46 secs Writing design to file "../p2.dir/3_3_2.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 4 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (12825) REAL time: 17 mins 25 secs Writing design to file "../p2.dir/3_3_2.ncd". Total REAL time: 17 mins 26 secs Total CPU time: 17 mins 23 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 29 secs Total CPU time to Router completion: 17 mins 26 secs Generating PAR statistics. Timing Score: 12825 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 22.191ns | 7 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_2.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 38 secs Total CPU time to PAR completion: 17 mins 34 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 3 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 8 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 815300 Placer score = 539684 Placer score = 506703 Placer score = 475935 Placer score = 431582 Placer score = 416564 Placer score = 406125 Placer score = 388749 Placer score = 372020 Placer score = 347439 Placer score = 336348 Placer score = 320029 Placer score = 292904 Placer score = 280958 Placer score = 279743 Placer score = 260663 Placer score = 250483 Placer score = 229182 Placer score = 214853 Placer score = 214570 Placer score = 212249 Placer score = 206119 Placer score = 204523 Placer score = 204474 Placer score = 199269 Placer score = 198087 Placer score = 197239 Placer score = 196860 Placer score = 194101 Placer score = 193329 Placer score = 193150 Placer score = 191753 Placer score = 189969 Placer score = 186243 Placer score = 185587 Placer score = 185284 Placer score = 184175 Placer score = 183665 Placer score = 183515 Finished Constructive Placer. REAL time: 8 mins 42 secs Writing design to file "../p2.dir/3_3_3.ncd". Starting Optimizing Placer. REAL time: 8 mins 43 secs Optimizing .. Swapped 20 comps. Xilinx Placer [5] 183185 REAL time: 9 mins 15 secs Optimizing .. Swapped 2 comps. Xilinx Placer [6] 183185 REAL time: 9 mins 47 secs Finished Optimizing Placer. REAL time: 9 mins 47 secs Writing design to file "../p2.dir/3_3_3.ncd". Total REAL time to Placer completion: 9 mins 48 secs Total CPU time to Placer completion: 9 mins 40 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 10 mins 6 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1404299) REAL time: 10 mins 42 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (21941) REAL time: 12 mins 4 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (11652) REAL time: 14 mins 10 secs End of iteration 4 3402 successful; 0 unrouted; (12849) REAL time: 15 mins 52 secs Writing design to file "../p2.dir/3_3_3.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (12167) REAL time: 17 mins 37 secs Writing design to file "../p2.dir/3_3_3.ncd". Total REAL time: 17 mins 37 secs Total CPU time: 17 mins 26 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 41 secs Total CPU time to Router completion: 17 mins 29 secs Generating PAR statistics. Timing Score: 12167 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 22.594ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_3.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 50 secs Total CPU time to PAR completion: 17 mins 38 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 4 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 8 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 13 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 767670 Placer score = 554754 Placer score = 494052 Placer score = 482749 Placer score = 441006 Placer score = 420693 Placer score = 394087 Placer score = 376782 Placer score = 371781 Placer score = 347295 Placer score = 337822 Placer score = 317504 Placer score = 291793 Placer score = 290677 Placer score = 277217 Placer score = 275058 Placer score = 261275 Placer score = 247153 Placer score = 246043 Placer score = 231940 Placer score = 220472 Placer score = 213074 Placer score = 212157 Placer score = 209844 Placer score = 205218 Placer score = 205200 Placer score = 203695 Placer score = 196593 Placer score = 195235 Placer score = 195005 Placer score = 193985 Placer score = 192847 Placer score = 191781 Placer score = 189345 Placer score = 188291 Placer score = 186238 Placer score = 186210 Placer score = 185489 Placer score = 184589 Placer score = 184289 Placer score = 184019 Placer score = 183839 Placer score = 183749 Finished Constructive Placer. REAL time: 8 mins 24 secs Writing design to file "../p2.dir/3_3_4.ncd". Starting Optimizing Placer. REAL time: 8 mins 25 secs Optimizing .. Swapped 16 comps. Xilinx Placer [7] 183509 REAL time: 8 mins 55 secs Optimizing .. Swapped 2 comps. Xilinx Placer [8] 183509 REAL time: 9 mins 25 secs Finished Optimizing Placer. REAL time: 9 mins 25 secs Writing design to file "../p2.dir/3_3_4.ncd". Total REAL time to Placer completion: 9 mins 26 secs Total CPU time to Placer completion: 9 mins 22 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 44 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (936049) REAL time: 10 mins 15 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (31877) REAL time: 11 mins 14 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 6 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (28855) REAL time: 13 mins 27 secs End of iteration 4 3402 successful; 0 unrouted; (27483) REAL time: 15 mins 5 secs Writing design to file "../p2.dir/3_3_4.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 6 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (26633) REAL time: 16 mins 29 secs Writing design to file "../p2.dir/3_3_4.ncd". Total REAL time: 16 mins 30 secs Total CPU time: 16 mins 20 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 16 mins 32 secs Total CPU time to Router completion: 16 mins 23 secs Generating PAR statistics. Timing Score: 26633 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 25.289ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_4.ncd". All signals are completely routed. Total REAL time to PAR completion: 16 mins 41 secs Total CPU time to PAR completion: 16 mins 31 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 5 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 788398 Placer score = 530418 Placer score = 495030 Placer score = 466275 Placer score = 430899 Placer score = 425341 Placer score = 400608 Placer score = 365196 Placer score = 349400 Placer score = 335007 Placer score = 315252 Placer score = 312796 Placer score = 288507 Placer score = 271534 Placer score = 264997 Placer score = 256090 Placer score = 241255 Placer score = 239754 Placer score = 228708 Placer score = 219047 Placer score = 209829 Placer score = 203224 Placer score = 200409 Placer score = 199079 Placer score = 195152 Placer score = 193814 Placer score = 190823 Placer score = 188960 Placer score = 188368 Placer score = 183889 Placer score = 182875 Placer score = 182396 Placer score = 180438 Placer score = 179878 Placer score = 178972 Placer score = 176638 Placer score = 175794 Placer score = 175225 Placer score = 175014 Placer score = 174835 Finished Constructive Placer. REAL time: 8 mins 39 secs Writing design to file "../p2.dir/3_3_5.ncd". Starting Optimizing Placer. REAL time: 8 mins 39 secs Optimizing .. Swapped 15 comps. Xilinx Placer [9] 174624 REAL time: 9 mins 10 secs Finished Optimizing Placer. REAL time: 9 mins 10 secs Writing design to file "../p2.dir/3_3_5.ncd". Total REAL time to Placer completion: 9 mins 11 secs Total CPU time to Placer completion: 9 mins 1 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 28 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1431796) REAL time: 9 mins 59 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (15212) REAL time: 11 mins 2 secs Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (12271) REAL time: 12 mins 54 secs End of iteration 4 3402 successful; 0 unrouted; (11404) REAL time: 14 mins 23 secs Writing design to file "../p2.dir/3_3_5.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (11404) REAL time: 16 mins 3 secs Writing design to file "../p2.dir/3_3_5.ncd". Total REAL time: 16 mins 3 secs Total CPU time: 15 mins 53 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 16 mins 6 secs Total CPU time to Router completion: 15 mins 56 secs Generating PAR statistics. Timing Score: 11404 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 23.492ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_5.ncd". All signals are completely routed. Total REAL time to PAR completion: 16 mins 15 secs Total CPU time to PAR completion: 16 mins 4 secs PAR done.