PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 09:28:32 1998 par -w -ol 3 -i 4 -t 1 -n 5 -s 5 map.ncd ../p2.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 2 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 785224 Placer score = 556279 Placer score = 548839 Placer score = 515641 Placer score = 455235 Placer score = 419573 Placer score = 394606 Placer score = 363926 Placer score = 330773 Placer score = 308476 Placer score = 288297 Placer score = 274068 Placer score = 266858 Placer score = 256095 Placer score = 245217 Placer score = 242668 Placer score = 232350 Placer score = 221529 Placer score = 219013 Placer score = 215839 Placer score = 209691 Placer score = 206894 Placer score = 206345 Placer score = 200805 Placer score = 200354 Placer score = 197967 Placer score = 195965 Placer score = 194355 Placer score = 192886 Placer score = 191419 Placer score = 189475 Placer score = 186941 Placer score = 186751 Placer score = 186345 Placer score = 185575 Placer score = 184643 Placer score = 184142 Placer score = 183962 Placer score = 183782 Placer score = 183482 Finished Constructive Placer. REAL time: 8 mins 26 secs Writing design to file "../p2.dir/3_3_2.ncd". Starting Optimizing Placer. REAL time: 8 mins 26 secs Optimizing .. Swapped 22 comps. Xilinx Placer [3] 183122 REAL time: 8 mins 57 secs Optimizing .. Swapped 8 comps. Xilinx Placer [4] 182942 REAL time: 9 mins 27 secs Finished Optimizing Placer. REAL time: 9 mins 27 secs Writing design to file "../p2.dir/3_3_2.ncd". Total REAL time to Placer completion: 9 mins 28 secs Total CPU time to Placer completion: 9 mins 26 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 45 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1949164) REAL time: 10 mins 19 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (26964) REAL time: 11 mins 35 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 4 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (13319) REAL time: 13 mins 48 secs End of iteration 4 3402 successful; 0 unrouted; (12998) REAL time: 15 mins 46 secs Writing design to file "../p2.dir/3_3_2.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 4 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (12825) REAL time: 17 mins 25 secs Writing design to file "../p2.dir/3_3_2.ncd". Total REAL time: 17 mins 26 secs Total CPU time: 17 mins 23 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 29 secs Total CPU time to Router completion: 17 mins 26 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 10972 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 3.965 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.157 ns The Maximum Pin Delay is: 26.404 ns The Average Connection Delay on the 10 Worst Nets is: 15.953 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3276 123 3 0 0 0 Timing Score: 12825 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 22.191ns | 7 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_2.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 38 secs Total CPU time to PAR completion: 17 mins 34 secs PAR done.