-------------------------------------------------------------------------------- Xilinx TRACE, Version M1.5.21 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: bdes.ncd Physical constraint file: bdes.pcf Device,speed: xc4010xl,-1 (x1_0.37 1.22 FINAL) Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_01 = PERIOD TIMEGRP "clk" 20 nS HIGH 50.000 % ; 7279 items analyzed, 10 timing errors detected. Minimum period is 22.191ns. -------------------------------------------------------------------------------- Slack: -2.191ns path U2160 to U2150 relative to 22.159ns total path delay 0.032ns clock skew 20.000ns delay constraint Path U2160 to U2150 contains 7 levels of logic: Path starting from Comp: CLB_R9C14.K (from n278) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R9C14.YQ Tcko 1.579R U2160 bootstrap/dma_cnt/iq_reg<2> CLB_R10C9.F4 net (fanout=5) 2.195R bs_addr<2> CLB_R10C9.Y Tiho 2.140R U2102 U4434/n2156 U4433/n2208 CLB_R10C10.F1 net (fanout=4) 0.824R n2208 CLB_R10C10.Y Tiho 2.140R U2128 U4196/n2054 U4195/n2052 CLB_R7C10.F3 net (fanout=4) 1.318R n2052 CLB_R7C10.X Tilo 1.300R U2130 U4123/n1889 CLB_R5C9.F3 net (fanout=4) 1.339R n1889 CLB_R5C9.Y Tiho 2.140R U2104 U4432/n2154 U4431/n2155 CLB_R8C10.F1 net (fanout=3) 1.882R n2155 CLB_R8C10.X Tilo 1.300R U1547 U2499/n1991 CLB_R5C14.F1 net (fanout=2) 2.252R n1991 CLB_R5C14.K Tihck 1.750R U2150 U3724 U3720 bootstrap/dma_cnt/iq_reg<18> ------------------------------------------------- Total (12.349ns logic, 9.810ns route) 22.159ns (to n278) (55.7% logic, 44.3% route) -------------------------------------------------------------------------------- Slack: -1.996ns path U2044 to U2150 relative to 21.964ns total path delay 0.032ns clock skew 20.000ns delay constraint Path U2044 to U2150 contains 7 levels of logic: Path starting from Comp: CLB_R4C8.K (from n278) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R4C8.XQ Tcko 1.579R U2044 bootstrap/dma_cnt/iq_reg<4> CLB_R10C9.C3 net (fanout=4) 2.290R bs_addr<4> CLB_R10C9.Y Thh1o 1.850R U2102 U4433/n2208 CLB_R10C10.F1 net (fanout=4) 0.824R n2208 CLB_R10C10.Y Tiho 2.140R U2128 U4196/n2054 U4195/n2052 CLB_R7C10.F3 net (fanout=4) 1.318R n2052 CLB_R7C10.X Tilo 1.300R U2130 U4123/n1889 CLB_R5C9.F3 net (fanout=4) 1.339R n1889 CLB_R5C9.Y Tiho 2.140R U2104 U4432/n2154 U4431/n2155 CLB_R8C10.F1 net (fanout=3) 1.882R n2155 CLB_R8C10.X Tilo 1.300R U1547 U2499/n1991 CLB_R5C14.F1 net (fanout=2) 2.252R n1991 CLB_R5C14.K Tihck 1.750R U2150 U3724 U3720 bootstrap/dma_cnt/iq_reg<18> ------------------------------------------------- Total (12.059ns logic, 9.905ns route) 21.964ns (to n278) (54.9% logic, 45.1% route) -------------------------------------------------------------------------------- Slack: -1.952ns path U2162 to U2150 relative to 20.000ns delay constraint Path U2162 to U2150 contains 7 levels of logic: Path starting from Comp: CLB_R4C9.K (from n278) To Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- -------- CLB_R4C9.XQ Tcko 1.579R U2162 bootstrap/dma_cnt/iq_reg<5> CLB_R10C9.C1 net (fanout=4) 2.138R bs_addr<5> CLB_R10C9.Y Thh0o 1.990R U2102 U4433/n2208 CLB_R10C10.F1 net (fanout=4) 0.824R n2208 CLB_R10C10.Y Tiho 2.140R U2128 U4196/n2054 U4195/n2052 CLB_R7C10.F3 net (fanout=4) 1.318R n2052 CLB_R7C10.X Tilo 1.300R U2130 U4123/n1889 CLB_R5C9.F3 net (fanout=4) 1.339R n1889 CLB_R5C9.Y Tiho 2.140R U2104 U4432/n2154 U4431/n2155 CLB_R8C10.F1 net (fanout=3) 1.882R n2155 CLB_R8C10.X Tilo 1.300R U1547 U2499/n1991 CLB_R5C14.F1 net (fanout=2) 2.252R n1991 CLB_R5C14.K Tihck 1.750R U2150 U3724 U3720 bootstrap/dma_cnt/iq_reg<18> ------------------------------------------------- Total (12.199ns logic, 9.753ns route) 21.952ns (to n278) (55.6% logic, 44.4% route) -------------------------------------------------------------------------------- 1 constraint not met. Table of Timegroups: ------------------- TimeGroup clk: BELs: bootstrap/dma_cnt/iq_reg<19> interrupt_source/q_reg<2> interrupt_source/divide_reg<1> bootstrap/wr_source/r10/q_reg<2> tod_receiver/tod_receiver/shift_reg_reg<11> memory_interface/rcp_1553_cs_n_reg synthesizer_interface/synth/shift_reg_reg<20> antenna_interface/ant/shift_reg_reg<0> audio_interface/aud/cycle_reg<2> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<4> fan_interface/pwm/shift_reg_reg<9> bootstrap/rx/sreg_reg<6> rtc_divide/clock_reg<5> external_port/rcp_reg1_reg audio_interface/aud/comm_sreg_reg<5> synthesizer_interface/synth/ser_clk_reg synthesizer_interface/sync_high/wren_reg tod_receiver/tod_receiver/shift_reg_reg<8> iic_bus_interface/iic/clock_reg<5> bootstrap/incr_addr_reg bootstrap/tx/baud_reg<7> audio_interface/aud/clock_reg<1> synthesizer_interface/synth/shift_reg_reg<4> synthesizer_interface/synth/shift_reg_reg<19> audio_interface/aud/data_sreg_reg<0> bootstrap/wr_source/r00/q_reg<0> synthesizer_interface/synth/clock_reg<3> bootstrap/wr_source/r12/q_reg<1> audio_interface/aud/ser_stb_reg iic_bus_interface/iic/shift_reg_reg<0> bootstrap/dma_cnt/iq_reg<3> bootstrap/wr_source/r02/q_reg<0> interrupt_source/q_reg<3> interrupt_source/divide_reg<0> bootstrap/wr_source/r10/q_reg<1> tod_receiver/tod_receiver/shift_reg_reg<10> bootstrap/tx/sreg_reg<0> internal_port/sync/wr_n_latch_reg tod_receiver/tod_receiver/manchester_decoder/edge_n_reg synthesizer_interface/synth/shift_reg_reg<21> antenna_interface/ant/shift_reg_reg<1> audio_interface/aud/cycle_reg<3> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<3> fan_interface/pwm/shift_reg_reg<8> synthesizer_interface/synth/cycle_reg<4> audio_interface/aud/busy_reg bootstrap/rx/sreg_reg<7> rtc_divide/clock_reg<6> internal_port/sync/ale_select_reg audio_interface/aud/comm_sreg_reg<4> tod_receiver/tod_receiver/shift_reg_reg<7> iic_bus_interface/iic/cycle_reg<0> synthesizer_interface/sync_high/wr_n_latch_reg iic_bus_interface/iic/clock_reg<4> bootstrap/tx/baud_reg<8> fill_output/fill_cc_dat_reg audio_interface/aud/clock_reg<2> tod_receiver/tod_receiver/manchester_decoder/sdai_1_reg synthesizer_interface/synth/shift_reg_reg<3> audio_interface/aud/data_sreg_reg<1> audio_interface/aud/free_clk_reg receiver_interface/dac/shift_reg_reg<9> bootstrap/wr_source/r00/q_reg<1> fan_interface/sync/ale_latch_reg bootstrap/wr_source/r12/q_reg<0> synthesizer_interface/synth/clock_reg<2> bootstrap/dma_cnt/iq_reg<2> bootstrap/wr_source/r02/q_reg<1> interrupt_source/q_reg<4> bootstrap/wr_source/r10/q_reg<0> bootstrap/tx/sreg_reg<1> memory_interface/dff_reg fan_interface/pwm/shift_reg_reg<10> synthesizer_interface/synth/shift_reg_reg<22> antenna_interface/ant/shift_reg_reg<2> audio_interface/aud/cycle_reg<4> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<2> fan_interface/pwm/shift_reg_reg<7> receiver_interface/sync/wr_n_latch_reg bootstrap/rx/busy_reg synthesizer_interface/synth/cycle_reg<3> synthesizer_interface/synth/ser_enbl_reg<0> rtc_divide/clock_reg<7> iic_bus_interface/iic/scl_reg audio_interface/aud/comm_sreg_reg<3> tod_receiver/tod_receiver/shift_reg_reg<6> iic_bus_interface/iic/cycle_reg<1> iic_bus_interface/iic/clock_reg<3> bootstrap/tx/baud_reg<9> audio_interface/aud/clock_reg<3> synthesizer_interface/synth/shift_reg_reg<2> audio_interface/aud/data_sreg_reg<2> receiver_interface/dac/shift_reg_reg<8> bootstrap/wr_source/r00/q_reg<2> synthesizer_interface/synth/clock_reg<1> bootstrap/dma_cnt/iq_reg<1> bootstrap/wr_source/r02/q_reg<2> fan_interface/pwm/clock_reg<0> interrupt_source/q_reg<5> bootstrap/tx/sreg_reg<2> bootstrap/rx/baud16_reg<6> fan_interface/pwm/shift_reg_reg<11> synthesizer_interface/synth/shift_reg_reg<23> antenna_interface/ant/shift_reg_reg<3> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<1> fan_interface/pwm/shift_reg_reg<6> synthesizer_interface/synth/cycle_reg<2> synthesizer_interface/synth/ser_enbl_reg<1> rtc_divide/clock_reg<8> audio_interface/aud/comm_sreg_reg<2> bootstrap/tx/int_busy_reg tod_receiver/tod_receiver/shift_reg_reg<5> iic_bus_interface/iic/cycle_reg<2> iic_bus_interface/iic/clock_reg<2> audio_interface/aud/clock_reg<4> synthesizer_interface/synth/shift_reg_reg<1> audio_interface/aud/data_sreg_reg<3> tod_receiver/tod_receiver/dinv_reg bootstrap/wr_source/r20/q_reg<0> bootstrap/wr_source/r23/q_reg<3> receiver_interface/dac/shift_reg_reg<7> bootstrap/wr_source/r00/q_reg<3> bootstrap/dma_cnt/iq_reg<10> synthesizer_interface/synth/clock_reg<0> receiver_interface/dac/ser_ld_n_reg bootstrap/wr_source/r22/q_reg<0> bootstrap/wr_source/r21/q_reg<3> bootstrap/dma_cnt/iq_reg<0> bootstrap/wr_source/r02/q_reg<3> bootstrap/rd_control/tx_strt_reg fan_interface/pwm/clock_reg<1> bootstrap/tx/sreg_reg<3> bootstrap/rx/baud16_reg<5> fan_interface/pwm/shift_reg_reg<12> tod_receiver/tod_receiver/manchester_decoder/stb_reg antenna_interface/ant/shift_reg_reg<4> bootstrap/rd_control/cycle_reg<3> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<0> bootstrap/rx/div16_reg<0> fan_interface/pwm/shift_reg_reg<5> iic_bus_interface/iic/stop_cycle_reg antenna_interface/ant/clock_reg<8> synthesizer_interface/synth/cycle_reg<1> synthesizer_interface/synth/ser_enbl_reg<2> rtc_divide/clock_reg<9> audio_interface/aud/comm_sreg_reg<1> synthesizer_interface/sync_low/ale_latch_reg tod_receiver/tod_receiver/shift_reg_reg<4> iic_bus_interface/iic/cycle_reg<3> tod_receiver/tod_receiver/manchester_decoder/sel_fall_reg synthesizer_interface/synth/shift_reg_reg<10> iic_bus_interface/iic/clock_reg<1> audio_interface/sync/ale_select_reg synthesizer_interface/synth/shift_reg_reg<0> audio_interface/aud/data_sreg_reg<4> bootstrap/wr_source/r20/q_reg<1> bootstrap/wr_source/r23/q_reg<2> iic_bus_interface/iic/shift_reg_reg<9> receiver_interface/dac/shift_reg_reg<6> fill_output/sync/ale_select_reg bootstrap/dma_cnt/iq_reg<11> bootstrap/decode/ext_reg<1> bootstrap/wr_source/r22/q_reg<1> bootstrap/wr_source/r21/q_reg<2> tod_receiver/sync/ale_latch_reg antenna_interface/ant/int_busy_reg fan_interface/pwm/clock_reg<2> bootstrap/tx/sreg_reg<4> bootstrap/rx/baud16_reg<4> receiver_interface/sync/ale_latch_reg external_port/sync/wr_n_latch_reg fan_interface/pwm/shift_reg_reg<13> receiver_interface/dac/clock_reg<0> antenna_interface/ant/shift_reg_reg<5> bootstrap/rd_control/cycle_reg<2> bootstrap/rx/div16_reg<1> fan_interface/pwm/shift_reg_reg<4> tod_receiver/sync/ale_select_reg iic_bus_interface/sync/ale_latch_reg tod_receiver/tod_receiver/manchester_decoder/sdai_2_reg antenna_interface/ant/clock_reg<7> synthesizer_interface/synth/cycle_reg<0> audio_interface/aud/comm_sreg_reg<0> tod_receiver/tod_receiver/shift_reg_reg<3> synthesizer_interface/synth/shift_reg_reg<11> synthesizer_interface/sync_low/ale_select_reg iic_bus_interface/iic/clock_reg<0> antenna_interface/ant/shift_reg_reg<10> audio_interface/aud/data_sreg_reg<5> bootstrap/wr_source/r20/q_reg<2> bootstrap/wr_source/r23/q_reg<1> iic_bus_interface/iic/shift_reg_reg<8> bootstrap/wr_control/cycle_reg<2> receiver_interface/dac/shift_reg_reg<5> bootstrap/dma_cnt/iq_reg<12> bootstrap/decode/ext_reg<0> bootstrap/wr_source/r22/q_reg<2> tod_receiver/tod_receiver/cycle_reg<3> bootstrap/wr_source/r21/q_reg<1> fan_interface/pwm/clock_reg<3> bootstrap/tx/sreg_reg<5> bootstrap/rx/baud16_reg<3> fan_interface/pwm/shift_reg_reg<14> receiver_interface/dac/cycle_reg<3> receiver_interface/dac/clock_reg<1> external_port/sync/ale_latch_reg antenna_interface/ant/shift_reg_reg<6> audio_interface/sync/wren_reg bootstrap/rd_control/cycle_reg<1> bootstrap/rx/div16_reg<2> fan_interface/pwm/shift_reg_reg<3> antenna_interface/ant/clock_reg<6> iic_bus_interface/iic/busy_reg bootstrap/tx/baud_reg<0> antenna_interface/sync/wr_n_latch_reg tod_receiver/tod_receiver/shift_reg_reg<2> synthesizer_interface/synth/shift_reg_reg<12> receiver_interface/dac/shift_reg_reg<10> antenna_interface/ant/shift_reg_reg<11> internal_port/sync/wren_reg bootstrap/wr_source/r03/q_reg<3> audio_interface/aud/data_sreg_reg<6> bootstrap/wr_source/r20/q_reg<3> bootstrap/wr_source/r23/q_reg<0> iic_bus_interface/iic/shift_reg_reg<7> fill_output/fill_req_reg bootstrap/wr_control/cycle_reg<1> receiver_interface/dac/shift_reg_reg<4> receiver_interface/dac/ser_clk_reg bootstrap/wr_source/r01/q_reg<3> bootstrap/dma_cnt/iq_reg<13> bootstrap/wr_source/r22/q_reg<3> bootstrap/wr_source/r21/q_reg<0> tod_receiver/tod_receiver/cycle_reg<2> fan_interface/pwm/clock_reg<4> bootstrap/tx/sreg_reg<6> iic_bus_interface/iic/shift_reg_reg<10> fan_interface/sync/wr_n_latch_reg tod_receiver/tod_receiver/manchester_decoder/timeout_reg<13> bootstrap/rx/baud16_reg<2> external_port/rcp_reg1_reg fan_interface/pwm/shift_reg_reg<15> receiver_interface/dac/cycle_reg<2> receiver_interface/dac/clock_reg<2> antenna_interface/ant/shift_reg_reg<7> bootstrap/rx/sreg_reg<0> bootstrap/rd_control/cycle_reg<0> bootstrap/rx/div16_reg<3> fan_interface/pwm/shift_reg_reg<2> external_port/sync/wren_reg antenna_interface/ant/clock_reg<5> bootstrap/rx/int_stb_reg bootstrap/tx/baud_reg<1> bootstrap/incr_en_reg tod_receiver/tod_receiver/shift_reg_reg<1> synthesizer_interface/synth/shift_reg_reg<13> receiver_interface/dac/shift_reg_reg<11> receiver_interface/sync/wren_reg antenna_interface/ant/shift_reg_reg<12> bootstrap/wr_source/r03/q_reg<2> antenna_interface/ant/cycle_reg<0> audio_interface/aud/data_sreg_reg<7> iic_bus_interface/iic/shift_reg_reg<6> bootstrap/dma_cnt/iq_reg<9> bootstrap/wr_control/cycle_reg<0> receiver_interface/dac/shift_reg_reg<3> bootstrap/wr_source/r01/q_reg<2> bootstrap/dma_cnt/iq_reg<14> tod_receiver/tod_receiver/cycle_reg<1> fan_interface/pwm/clock_reg<5> fill_output/sync/wren_reg bootstrap/tx/sreg_reg<7> iic_bus_interface/iic/shift_reg_reg<11> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<12> bootstrap/rx/baud16_reg<1> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<9> fan_interface/pwm/shift_reg_reg<16> receiver_interface/dac/cycle_reg<1> receiver_interface/dac/clock_reg<3> audio_interface/aud/ser_doe_n_reg antenna_interface/ant/shift_reg_reg<8> iic_bus_interface/sync/wr_n_latch_reg bootstrap/rx/sreg_reg<1> synthesizer_interface/sync_high/ale_select_reg fan_interface/sync/ale_select_reg rtc_divide/clock_reg<0> fan_interface/pwm/shift_reg_reg<1> bootstrap/decode/int_active_reg antenna_interface/ant/clock_reg<4> synthesizer_interface/sync_high/ale_latch_reg bootstrap/wr_control/cycle_rst_n_reg interrupt_source/intr_reg iic_bus_interface/sync/wren_reg bootstrap/tx/baud_reg<2> antenna_interface/sync/ale_latch_reg tod_receiver/sync/wren_reg tod_receiver/tod_receiver/shift_reg_reg<0> synthesizer_interface/synth/shift_reg_reg<9> synthesizer_interface/synth/shift_reg_reg<14> receiver_interface/dac/shift_reg_reg<12> antenna_interface/ant/shift_reg_reg<13> receiver_interface/dac/busy_reg bootstrap/wr_source/r03/q_reg<1> antenna_interface/ant/cycle_reg<1> iic_bus_interface/iic/shift_reg_reg<5> bootstrap/dma_cnt/iq_reg<8> bootstrap/wr_source/r11/q_reg<0> receiver_interface/dac/shift_reg_reg<2> internal_port/rcp_reg2_reg bootstrap/wr_source/r01/q_reg<1> bootstrap/dma_cnt/iq_reg<15> tod_receiver/tod_receiver/shift_reg_reg<15> bootstrap/rx/cycle_reg<3> fill_output/fill_clk_reg receiver_interface/sync/ale_select_reg tod_receiver/tod_receiver/cycle_reg<0> bootstrap/wr_source/r13/q_reg<0> fan_interface/pwm/clock_reg<6> bootstrap/tx/sreg_reg<8> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<11> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<8> bootstrap/rx/baud16_reg<0> bootstrap/wr_control/wr_n_reg fan_interface/pwm/shift_reg_reg<17> receiver_interface/dac/cycle_reg<0> antenna_interface/ant/shift_reg_reg<9> bootstrap/tx/cycle_reg<0> bootstrap/rx/sreg_reg<2> rtc_divide/clock_reg<1> fan_interface/pwm/shift_reg_reg<0> antenna_interface/ant/clock_reg<3> synthesizer_interface/synth/int_busy_reg bootstrap/tx/baud_reg<3> synthesizer_interface/synth/shift_reg_reg<8> synthesizer_interface/synth/shift_reg_reg<15> antenna_interface/ant/shift_reg_reg<14> audio_interface/aud/read_cycle_reg bootstrap/wr_source/r03/q_reg<0> antenna_interface/ant/cycle_reg<2> iic_bus_interface/iic/shift_reg_reg<4> bootstrap/dma_cnt/iq_reg<7> bootstrap/wr_source/r11/q_reg<1> rtc_divide/clk_reg receiver_interface/dac/shift_reg_reg<1> internal_port/rcp_reg2_reg bootstrap/wr_source/r01/q_reg<0> bootstrap/dma_cnt/iq_reg<16> tod_receiver/tod_receiver/shift_reg_reg<14> bootstrap/rx/cycle_reg<2> bootstrap/wr_source/r13/q_reg<1> iic_bus_interface/iic/read_cycle_reg fan_interface/pwm/clock_reg<7> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<10> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<7> audio_interface/sync/ale_latch_reg bootstrap/tx/cycle_reg<1> bootstrap/rx/sreg_reg<3> rtc_divide/clock_reg<2> fan_interface/sync/wren_reg tod_receiver/tod_receiver/manchester_decoder/to_dff_reg antenna_interface/ant/clock_reg<2> bootstrap/tx/baud_reg<4> synthesizer_interface/synth/shift_reg_reg<7> synthesizer_interface/synth/shift_reg_reg<16> antenna_interface/ant/shift_reg_reg<15> antenna_interface/sync/wren_reg antenna_interface/ant/cycle_reg<3> iic_bus_interface/iic/shift_reg_reg<3> bootstrap/dma_cnt/iq_reg<6> bootstrap/wr_source/r11/q_reg<2> receiver_interface/dac/shift_reg_reg<0> iic_bus_interface/sync/ale_select_reg bootstrap/dma_cnt/iq_reg<17> interrupt_source/q_reg<0> tod_receiver/tod_receiver/shift_reg_reg<13> bootstrap/rx/cycle_reg<1> tod_receiver/tod_receiver/active_reg audio_interface/sync/wr_n_latch_reg bootstrap/wr_source/r13/q_reg<2> fan_interface/pwm/clock_reg<8> audio_interface/aud/cycle_reg<0> tod_receiver/tod_receiver/manchester_decoder/timeout_reg<6> tod_receiver/tod_en_reg receiver_interface/dac/ser_dato_reg bootstrap/tx/cycle_reg<2> bootstrap/rx/sreg_reg<4> rtc_divide/clock_reg<3> external_port/rcp_reg1_reg audio_interface/aud/comm_sreg_reg<7> antenna_interface/ant/clock_reg<1> iic_bus_interface/iic/sda_oe_n_reg fill_output/sync/wr_n_latch_reg antenna_interface/ant/ser_clk_reg iic_bus_interface/iic/clock_reg<7> bootstrap/tx/baud_reg<5> tod_receiver/sync/wr_n_latch_reg synthesizer_interface/synth/shift_reg_reg<6> synthesizer_interface/synth/shift_reg_reg<17> fan_interface/pwm/clock_reg<10> synthesizer_interface/sync_low/wren_reg antenna_interface/ant/cycle_reg<4> external_port/sync/ale_select_reg bootstrap/wr_source/r12/q_reg<3> iic_bus_interface/iic/shift_reg_reg<2> bootstrap/dma_cnt/iq_reg<5> bootstrap/wr_source/r11/q_reg<3> synthesizer_interface/sync_low/wr_n_latch_reg bootstrap/dma_cnt/iq_reg<18> interrupt_source/q_reg<1> bootstrap/wr_source/r10/q_reg<3> tod_receiver/tod_receiver/shift_reg_reg<12> bootstrap/rx/cycle_reg<0> bootstrap/wr_source/r13/q_reg<3> fan_interface/pwm/clock_reg<9> tod_receiver/tod_receiver/stb_reg bootstrap/rd_control/cyc_rst_n_reg audio_interface/aud/cycle_reg<1> external_port/rcp_reg1_reg tod_receiver/tod_receiver/manchester_decoder/timeout_reg<5> bootstrap/tx/baud_reg<10> internal_port/sync/ale_latch_reg bootstrap/tx/cycle_reg<3> bootstrap/rx/sreg_reg<5> rtc_divide/clock_reg<4> external_port/rcp_reg1_reg audio_interface/aud/comm_sreg_reg<6> antenna_interface/ant/clock_reg<0> tod_receiver/tod_receiver/shift_reg_reg<9> antenna_interface/sync/ale_select_reg iic_bus_interface/iic/clock_reg<6> bootstrap/tx/baud_reg<6> audio_interface/aud/clock_reg<0> synthesizer_interface/synth/shift_reg_reg<5> synthesizer_interface/synth/shift_reg_reg<18> fill_output/sync/ale_latch_reg fan_interface/pwm/clock_reg<11> synthesizer_interface/synth/clock_reg<4> bootstrap/wr_source/r12/q_reg<2> iic_bus_interface/iic/shift_reg_reg<1> bootstrap/dma_cnt/iq_reg<4> external_port/rcp_reg1_reg Timing summary: --------------- Timing errors: 10 Score: 12825 Constraints cover 7720 paths, 0 nets, and 2846 connections (83.7% coverage) Design statistics: Minimum period: 22.191ns (Maximum frequency: 45.063MHz) Analysis completed Tue Oct 06 15:23:15 1998 --------------------------------------------------------------------------------