PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 09:46:09 1998 par -w -ol 3 -i 4 -t 1 -n 5 -s 5 map.ncd ../p2.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 3 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 8 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 815300 Placer score = 539684 Placer score = 506703 Placer score = 475935 Placer score = 431582 Placer score = 416564 Placer score = 406125 Placer score = 388749 Placer score = 372020 Placer score = 347439 Placer score = 336348 Placer score = 320029 Placer score = 292904 Placer score = 280958 Placer score = 279743 Placer score = 260663 Placer score = 250483 Placer score = 229182 Placer score = 214853 Placer score = 214570 Placer score = 212249 Placer score = 206119 Placer score = 204523 Placer score = 204474 Placer score = 199269 Placer score = 198087 Placer score = 197239 Placer score = 196860 Placer score = 194101 Placer score = 193329 Placer score = 193150 Placer score = 191753 Placer score = 189969 Placer score = 186243 Placer score = 185587 Placer score = 185284 Placer score = 184175 Placer score = 183665 Placer score = 183515 Finished Constructive Placer. REAL time: 8 mins 42 secs Writing design to file "../p2.dir/3_3_3.ncd". Starting Optimizing Placer. REAL time: 8 mins 43 secs Optimizing .. Swapped 20 comps. Xilinx Placer [5] 183185 REAL time: 9 mins 15 secs Optimizing .. Swapped 2 comps. Xilinx Placer [6] 183185 REAL time: 9 mins 47 secs Finished Optimizing Placer. REAL time: 9 mins 47 secs Writing design to file "../p2.dir/3_3_3.ncd". Total REAL time to Placer completion: 9 mins 48 secs Total CPU time to Placer completion: 9 mins 40 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 10 mins 6 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1404299) REAL time: 10 mins 42 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (21941) REAL time: 12 mins 4 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (11652) REAL time: 14 mins 10 secs End of iteration 4 3402 successful; 0 unrouted; (12849) REAL time: 15 mins 52 secs Writing design to file "../p2.dir/3_3_3.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 1 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (12167) REAL time: 17 mins 37 secs Writing design to file "../p2.dir/3_3_3.ncd". Total REAL time: 17 mins 37 secs Total CPU time: 17 mins 26 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 17 mins 41 secs Total CPU time to Router completion: 17 mins 29 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 10025 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 4.287 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.177 ns The Maximum Pin Delay is: 20.408 ns The Average Connection Delay on the 10 Worst Nets is: 17.691 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3217 181 4 0 0 0 Timing Score: 12167 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 22.594ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_3.ncd". All signals are completely routed. Total REAL time to PAR completion: 17 mins 50 secs Total CPU time to PAR completion: 17 mins 38 secs PAR done.