PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 10:20:40 1998 par -w -ol 3 -i 4 -t 1 -n 5 -s 5 map.ncd ../p2.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 3 (set by user) Placer effort level (-pl): 3 (default) Placer cost table entry (-t): 5 Router effort level (-rl): 3 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 788398 Placer score = 530418 Placer score = 495030 Placer score = 466275 Placer score = 430899 Placer score = 425341 Placer score = 400608 Placer score = 365196 Placer score = 349400 Placer score = 335007 Placer score = 315252 Placer score = 312796 Placer score = 288507 Placer score = 271534 Placer score = 264997 Placer score = 256090 Placer score = 241255 Placer score = 239754 Placer score = 228708 Placer score = 219047 Placer score = 209829 Placer score = 203224 Placer score = 200409 Placer score = 199079 Placer score = 195152 Placer score = 193814 Placer score = 190823 Placer score = 188960 Placer score = 188368 Placer score = 183889 Placer score = 182875 Placer score = 182396 Placer score = 180438 Placer score = 179878 Placer score = 178972 Placer score = 176638 Placer score = 175794 Placer score = 175225 Placer score = 175014 Placer score = 174835 Finished Constructive Placer. REAL time: 8 mins 39 secs Writing design to file "../p2.dir/3_3_5.ncd". Starting Optimizing Placer. REAL time: 8 mins 39 secs Optimizing .. Swapped 15 comps. Xilinx Placer [9] 174624 REAL time: 9 mins 10 secs Finished Optimizing Placer. REAL time: 9 mins 10 secs Writing design to file "../p2.dir/3_3_5.ncd". Total REAL time to Placer completion: 9 mins 11 secs Total CPU time to Placer completion: 9 mins 1 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 9 mins 28 secs Starting iterative routing. Routing active signals. End of iteration 1 3402 successful; 0 unrouted; (1431796) REAL time: 9 mins 59 secs Improving timing. End of iteration 2 3402 successful; 0 unrouted; (15212) REAL time: 11 mins 2 secs Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (12271) REAL time: 12 mins 54 secs End of iteration 4 3402 successful; 0 unrouted; (11404) REAL time: 14 mins 23 secs Writing design to file "../p2.dir/3_3_5.ncd". Starting cleanup Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (11404) REAL time: 16 mins 3 secs Writing design to file "../p2.dir/3_3_5.ncd". Total REAL time: 16 mins 3 secs Total CPU time: 15 mins 53 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 16 mins 6 secs Total CPU time to Router completion: 15 mins 56 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 12944 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 3.971 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.200 ns The Maximum Pin Delay is: 19.974 ns The Average Connection Delay on the 10 Worst Nets is: 15.949 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3268 134 0 0 0 0 Timing Score: 11404 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 23.492ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p2.dir/3_3_5.ncd". All signals are completely routed. Total REAL time to PAR completion: 16 mins 15 secs Total CPU time to PAR completion: 16 mins 4 secs PAR done.