ngdbuild -p xc4010xl-1-pq208 -uc C:\davin\1097\englabs\bdes2\bdes.ucf -dd .. C:\davin\1097\englabs\bdes2\bdes.xtf bdes.ngd ngdbuild: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -p xc4010xl-1-pq208 -uc C:\davin\1097\englabs\bdes2\bdes.ucf -dd .. C:\davin\1097\englabs\bdes2\bdes.xtf bdes.ngd Launcher: "bdes.ngo" is up to date. Reading NGO file "C:/davin/1097/englabs/bdes2/xproj/ver1_proto/bdes.ngo" ... Reading component libraries for design expansion... Annotating constraints to design from file "C:/davin/1097/englabs/bdes2/bdes.ucf" ... Checking timing specifications ... Checking expanded design ... WARNING:basnu:147 - clock net "address_generator/n31<0>" has non-clock connections WARNING:basnu:148 - clock net "address_generator/n31<0>" drives no clock pins NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 2 Writing NGD file "bdes.ngd" ... Writing NGDBUILD log file "bdes.bld"... NGDBUILD done. ================================================== map -p xc4010xl-1-pq208 -o map.ncd bdes.ngd bdes.pcf map: version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Reading NGD file "bdes.ngd"... Using target part "4010xlpq208-1". MAP xc4000xl directives: Partname = "xc4010xl-1-pq208". Covermode = "area". Pack CLBs to 100%. Processing logical timing constraints... Verifying F/HMAP validity based on pre-trimmed logic... Removing unused logic... Packing logic in CLBs... Running cover... Undirected packing... Running physical design DRC... Design Summary: Number of errors: 0 Number of warnings: 2 Number of CLBs: 350 out of 400 87% CLB Flip Flops: 441 CLB Latches: 0 4 input LUTs: 657 (41 used as route-throughs) 3 input LUTs: 153 (36 used as route-throughs) Number of bonded IOBs: 105 out of 160 65% IOB Flops: 0 IOB Latches: 0 Number of clock IOB pads: 2 out of 12 16% Number of BUFGLSs: 2 out of 8 25% Total equivalent gate count for design: 6868 Additional JTAG gate count for IOBs: 5040 Writing design file "map.ncd"... Removed Logic Summary: Mapping completed. See MAP report file "map.mrp" for details. ================================================== par -w -ol 1 -i 4 -t 1 -n 5 -s 5 map.ncd ../p3.dir bdes.pcf PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Resolving physical constraints. Finished resolving physical constraints. Writing design to file "C:/TEMP/xil_93". Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 16 secs Finished initial Placement phase. REAL time: 16 secs Starting Constructive Placer. REAL time: 17 secs Placer score = 778397 Placer score = 555523 Placer score = 524465 Placer score = 438402 Placer score = 385322 Placer score = 368122 Placer score = 324895 Placer score = 314068 Placer score = 292081 Placer score = 272769 Placer score = 264131 Placer score = 252924 Placer score = 241920 Placer score = 241558 Placer score = 235878 Placer score = 233853 Placer score = 230058 Placer score = 228971 Placer score = 226871 Placer score = 225910 Finished Constructive Placer. REAL time: 2 mins 26 secs Writing design to file "../p3.dir/1_1_1.ncd". Total REAL time to Placer completion: 2 mins 27 secs Total CPU time to Placer completion: 2 mins 25 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 44 secs Starting iterative routing. Routing active signals. End of iteration 1 3343 successful; 59 unrouted; (5264597) REAL time: 6 mins 17 secs End of iteration 2 3401 successful; 1 unrouted; (3488756) REAL time: 8 mins 25 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. End of iteration 3 3402 successful; 0 unrouted; (323663) REAL time: 10 mins 8 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 4 3402 successful; 0 unrouted; (208121) REAL time: 12 mins 17 secs Writing design to file "../p3.dir/1_1_1.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (207682) REAL time: 13 mins 35 secs Writing design to file "../p3.dir/1_1_1.ncd". Total REAL time: 13 mins 36 secs Total CPU time: 13 mins 34 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 13 mins 39 secs Total CPU time to Router completion: 13 mins 37 secs Generating PAR statistics. Timing Score: 207682 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 29.716ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_1.ncd". All signals are completely routed. Total REAL time to PAR completion: 13 mins 48 secs Total CPU time to PAR completion: 13 mins 46 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 2 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 717183 Placer score = 490003 Placer score = 452386 Placer score = 397502 Placer score = 344472 Placer score = 337892 Placer score = 306910 Placer score = 297651 Placer score = 274977 Placer score = 257873 Placer score = 256596 Placer score = 249163 Placer score = 244032 Placer score = 243193 Placer score = 239952 Placer score = 239187 Placer score = 236079 Placer score = 234475 Placer score = 233417 Placer score = 229440 Placer score = 228660 Placer score = 228150 Placer score = 227850 Finished Constructive Placer. REAL time: 2 mins 22 secs Writing design to file "../p3.dir/1_1_2.ncd". Total REAL time to Placer completion: 2 mins 23 secs Total CPU time to Placer completion: 2 mins 21 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 40 secs Starting iterative routing. Routing active signals. End of iteration 1 3341 successful; 61 unrouted; (12561997) REAL time: 6 mins 25 secs End of iteration 2 3401 successful; 1 unrouted; (2087732) REAL time: 8 mins 24 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 6 timing errors. End of iteration 3 3401 successful; 1 unrouted; (925093) REAL time: 9 mins 58 secs End of iteration 4 3402 successful; 0 unrouted; (550368) REAL time: 11 mins 24 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. Writing design to file "../p3.dir/1_1_2.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 7 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (358836) REAL time: 12 mins 47 secs Writing design to file "../p3.dir/1_1_2.ncd". Total REAL time: 12 mins 48 secs Total CPU time: 12 mins 45 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 12 mins 51 secs Total CPU time to Router completion: 12 mins 48 secs Generating PAR statistics. Timing Score: 358836 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 33.784ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_2.ncd". All signals are completely routed. Total REAL time to PAR completion: 13 mins Total CPU time to PAR completion: 12 mins 57 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 3 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 791361 Placer score = 500026 Placer score = 461495 Placer score = 406093 Placer score = 355023 Placer score = 340659 Placer score = 312635 Placer score = 305433 Placer score = 278814 Placer score = 262681 Placer score = 257580 Placer score = 249731 Placer score = 241372 Placer score = 239539 Placer score = 238713 Placer score = 233842 Placer score = 232111 Placer score = 231234 Finished Constructive Placer. REAL time: 2 mins 13 secs Writing design to file "../p3.dir/1_1_3.ncd". Total REAL time to Placer completion: 2 mins 15 secs Total CPU time to Placer completion: 2 mins 14 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 31 secs Starting iterative routing. Routing active signals. End of iteration 1 3349 successful; 53 unrouted; (5661364) REAL time: 6 mins End of iteration 2 3401 successful; 1 unrouted; (3976399) REAL time: 7 mins 56 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 4 timing errors. End of iteration 3 3402 successful; 0 unrouted; (1012299) REAL time: 9 mins 35 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 4 3402 successful; 0 unrouted; (666676) REAL time: 11 mins 45 secs Writing design to file "../p3.dir/1_1_3.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (395005) REAL time: 12 mins 59 secs Writing design to file "../p3.dir/1_1_3.ncd". Total REAL time: 13 mins Total CPU time: 12 mins 59 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 13 mins 3 secs Total CPU time to Router completion: 13 mins 2 secs Generating PAR statistics. Timing Score: 395005 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 33.896ns | 4 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_3.ncd". All signals are completely routed. Total REAL time to PAR completion: 13 mins 12 secs Total CPU time to PAR completion: 13 mins 10 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 4 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 11 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 12 secs Placer score = 835826 Placer score = 597017 Placer score = 494646 Placer score = 431476 Placer score = 382236 Placer score = 371680 Placer score = 335201 Placer score = 323335 Placer score = 301413 Placer score = 283145 Placer score = 282086 Placer score = 269947 Placer score = 262875 Placer score = 258860 Placer score = 253658 Placer score = 249507 Placer score = 248034 Placer score = 243213 Placer score = 241160 Placer score = 240347 Placer score = 239200 Finished Constructive Placer. REAL time: 2 mins 29 secs Writing design to file "../p3.dir/1_1_4.ncd". Total REAL time to Placer completion: 2 mins 30 secs Total CPU time to Placer completion: 2 mins 29 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 47 secs Starting iterative routing. Routing active signals. End of iteration 1 3335 successful; 67 unrouted; (6230283) REAL time: 6 mins 57 secs End of iteration 2 3401 successful; 1 unrouted; (3818727) REAL time: 9 mins 4 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 6 timing errors. End of iteration 3 3402 successful; 0 unrouted; (521340) REAL time: 10 mins 47 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 4 3402 successful; 0 unrouted; (391332) REAL time: 12 mins 55 secs Writing design to file "../p3.dir/1_1_4.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 6 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (389964) REAL time: 14 mins 4 secs Writing design to file "../p3.dir/1_1_4.ncd". Total REAL time: 14 mins 5 secs Total CPU time: 14 mins 4 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 14 mins 8 secs Total CPU time to Router completion: 14 mins 7 secs Generating PAR statistics. Timing Score: 389964 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 32.085ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_4.ncd". All signals are completely routed. Total REAL time to PAR completion: 14 mins 17 secs Total CPU time to PAR completion: 14 mins 15 secs PAR done. Constraints file: bdes.pcf Loading device database for application par from file "C:/TEMP/xil_93". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 5 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 7 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 12 secs Finished initial Placement phase. REAL time: 12 secs Starting Constructive Placer. REAL time: 13 secs Placer score = 790036 Placer score = 504823 Placer score = 455629 Placer score = 391893 Placer score = 352523 Placer score = 344856 Placer score = 313529 Placer score = 297418 Placer score = 283129 Placer score = 271210 Placer score = 265519 Placer score = 261311 Placer score = 261120 Placer score = 259151 Placer score = 255981 Placer score = 252864 Placer score = 251473 Placer score = 250229 Finished Constructive Placer. REAL time: 2 mins 9 secs Writing design to file "../p3.dir/1_1_5.ncd". Total REAL time to Placer completion: 2 mins 10 secs Total CPU time to Placer completion: 2 mins 9 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 25 secs Starting iterative routing. Routing active signals. End of iteration 1 3350 successful; 52 unrouted; (5383114) REAL time: 5 mins 30 secs End of iteration 2 3402 successful; 0 unrouted; (2097150) REAL time: 7 mins 51 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 7 timing errors. Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 3 3402 successful; 0 unrouted; (735008) REAL time: 10 mins 16 secs End of iteration 4 3402 successful; 0 unrouted; (576483) REAL time: 12 mins 23 secs Writing design to file "../p3.dir/1_1_5.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 7 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (523454) REAL time: 13 mins 36 secs Writing design to file "../p3.dir/1_1_5.ncd". Total REAL time: 13 mins 36 secs Total CPU time: 13 mins 35 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 13 mins 40 secs Total CPU time to Router completion: 13 mins 38 secs Generating PAR statistics. Timing Score: 523454 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 35.969ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_5.ncd". All signals are completely routed. Total REAL time to PAR completion: 13 mins 47 secs Total CPU time to PAR completion: 13 mins 45 secs PAR done.