PAR: Xilinx Place And Route M1.5.20. Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Tue Oct 06 10:40:31 1998 par -w -ol 1 -i 4 -t 1 -n 5 -s 5 map.ncd ../p3.dir bdes.pcf Constraints file: bdes.pcf Loading device database for application par from file "map.ncd". "bdes" is an NCD, version 2.27, device xc4010xl, package pq208, speed -1 Loading device for application par from file '4010xl.nph' in environment C:/fndtn. Device speed data version: x1_0.37 1.22 FINAL. Writing design to file "C:/TEMP/xil_93". Device utilization summary: Number of External IOBs 103 out of 160 64% Flops: 0 Latches: 0 Number of Global Buffer IOBs 2 out of 8 25% Flops: 0 Latches: 0 Number of CLBs 350 out of 400 87% Total Latches: 0 out of 800 0% Total CLB Flops: 441 out of 800 55% 4 input LUTs: 657 out of 800 82% 3 input LUTs: 153 out of 400 38% Number of BUFGLSs 2 out of 8 25% Overall effort level (-ol): 1 (set by user) Placer effort level (-pl): 1 (default) Placer cost table entry (-t): 1 Router effort level (-rl): 1 (default) Timing method (-kpaths|-dfs): -kpaths (default) Starting initial Timing Analysis. REAL time: 9 secs Finished initial Timing Analysis. REAL time: 13 secs Starting initial Placement phase. REAL time: 16 secs Finished initial Placement phase. REAL time: 16 secs Starting Constructive Placer. REAL time: 17 secs Placer score = 778397 Placer score = 555523 Placer score = 524465 Placer score = 438402 Placer score = 385322 Placer score = 368122 Placer score = 324895 Placer score = 314068 Placer score = 292081 Placer score = 272769 Placer score = 264131 Placer score = 252924 Placer score = 241920 Placer score = 241558 Placer score = 235878 Placer score = 233853 Placer score = 230058 Placer score = 228971 Placer score = 226871 Placer score = 225910 Finished Constructive Placer. REAL time: 2 mins 26 secs Writing design to file "../p3.dir/1_1_1.ncd". Total REAL time to Placer completion: 2 mins 27 secs Total CPU time to Placer completion: 2 mins 25 secs 0 connection(s) routed; 3402 unrouted. Starting router resource preassignment Completed router resource preassignment. REAL time: 2 mins 44 secs Starting iterative routing. Routing active signals. End of iteration 1 3343 successful; 59 unrouted; (5264597) REAL time: 6 mins 17 secs End of iteration 2 3401 successful; 1 unrouted; (3488756) REAL time: 8 mins 25 secs WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. End of iteration 3 3402 successful; 0 unrouted; (323663) REAL time: 10 mins 8 secs Improving timing. Routing PWR/GND nets. Power and ground nets completely routed. End of iteration 4 3402 successful; 0 unrouted; (208121) REAL time: 12 mins 17 secs Writing design to file "../p3.dir/1_1_1.ncd". Starting cleanup WARNING:basrt:188 - Routing for this placement can not meet all timing constraints. It may have as many as 5 timing errors. Improving routing. End of cleanup iteration 1 3402 successful; 0 unrouted; (207682) REAL time: 13 mins 35 secs Writing design to file "../p3.dir/1_1_1.ncd". Total REAL time: 13 mins 36 secs Total CPU time: 13 mins 34 secs End of route. 3402 routed (100.00%); 0 unrouted. No errors found. Completely routed. The design submitted for place and route did not meet the specified timing requirements. Please use the static timing analysis tools (TRCE or Timing Analyzer) to report which constraints were not met. To obtain a better result, you may try the following: * Use the Re-entrant routing feature to run more router iterations on the design. * Check the timing constraints to make sure the design is not over-constrained. * Specify a higher placer effort level, if possible. * Specify a higher router effort level. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement trials from which the best (i.e., lowest design score) placement can be used with re-entrant routing to obtain a better result. Please consult the Development System Reference Guide for more detailed information about the usage options pertaining to these features. Total REAL time to Router completion: 13 mins 39 secs Total CPU time to Router completion: 13 mins 37 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 106097 The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 4.779 ns The Average Connection Delay on critical nets is: 0.000 ns The Average Clock Skew for this design is: 0.175 ns The Maximum Pin Delay is: 27.698 ns The Average Connection Delay on the 10 Worst Nets is: 23.292 ns Listing Pin Delays by value: (ns) d <= 10 < d <= 20 < d <= 30 < d <= 40 < d <= 50 d > 50 --------- --------- --------- --------- --------- --------- 3149 228 25 0 0 0 Timing Score: 207682 WARNING:baspw:101 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met. -------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels -------------------------------------------------------------------------------- * TS_01 = PERIOD TIMEGRP "clk" 20 nS HIG | 20.000ns | 29.716ns | 8 H 50.000 % | | | -------------------------------------------------------------------------------- 1 constraint not met. Writing design to file "../p3.dir/1_1_1.ncd". All signals are completely routed. Total REAL time to PAR completion: 13 mins 48 secs Total CPU time to PAR completion: 13 mins 46 secs PAR done.